Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi_gnvs.h> |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <arch/smp/mpspec.h> |
| 6 | #include <assert.h> |
| 7 | #include <cbmem.h> |
| 8 | #include <cpu/intel/turbo.h> |
| 9 | #include <device/mmio.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <intelblocks/acpi.h> |
| 12 | #include <soc/acpi.h> |
| 13 | #include <soc/cpu.h> |
| 14 | #include <soc/iomap.h> |
| 15 | #include <soc/msr.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/pm.h> |
| 18 | #include <soc/soc_util.h> |
| 19 | |
| 20 | #include "chip.h" |
| 21 | |
| 22 | /* TODO: Check if the common/acpi weak function can be used */ |
| 23 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 24 | { |
| 25 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 26 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); |
| 27 | return current; |
| 28 | } |
| 29 | |
| 30 | void acpi_create_gnvs(struct global_nvs *gnvs) |
| 31 | { |
| 32 | /* CPU core count */ |
| 33 | gnvs->pcnt = dev_count_cpu(); |
| 34 | printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); |
| 35 | } |
| 36 | |
| 37 | int soc_madt_sci_irq_polarity(int sci) |
| 38 | { |
| 39 | if (sci >= 20) |
| 40 | return MP_IRQ_POLARITY_LOW; |
| 41 | else |
| 42 | return MP_IRQ_POLARITY_HIGH; |
| 43 | } |
| 44 | |
Marc Jones | 70ddbd8 | 2020-09-28 12:25:03 -0600 | [diff] [blame^] | 45 | uint32_t soc_read_sci_irq_select(void) |
| 46 | { |
| 47 | struct device *dev = PCH_DEV_PMC; |
| 48 | |
| 49 | if (!dev) |
| 50 | return 0; |
| 51 | |
| 52 | return pci_read_config32(dev, PMC_ACPI_CNT); |
| 53 | } |
| 54 | |
Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 55 | /* |
| 56 | * Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt() |
| 57 | * with a call from the common/function or find another way to call this at the correct place |
| 58 | */ |
| 59 | void uncore_inject_dsdt(void) |
| 60 | { |
| 61 | struct iiostack_resource stack_info = {0}; |
| 62 | |
| 63 | get_iiostack_info(&stack_info); |
| 64 | |
| 65 | acpigen_write_scope("\\_SB"); |
| 66 | |
| 67 | for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) { |
| 68 | const STACK_RES *ri = &stack_info.res[stack]; |
| 69 | char rtname[16]; |
| 70 | |
| 71 | snprintf(rtname, sizeof(rtname), "RT%02x", stack); |
| 72 | |
| 73 | acpigen_write_name(rtname); |
| 74 | printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n", |
| 75 | rtname, stack); |
| 76 | |
| 77 | acpigen_write_resourcetemplate_header(); |
| 78 | |
| 79 | /* bus resource */ |
| 80 | acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, |
| 81 | 0x0, (ri->BusLimit - ri->BusBase + 1)); |
| 82 | |
| 83 | /* additional io resources on socket 0 bus 0 */ |
| 84 | if (stack == 0) { |
| 85 | /* ACPI 6.4.2.5 I/O Port Descriptor */ |
| 86 | acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); |
| 87 | |
| 88 | /* IO decode CF8-CFF */ |
| 89 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); |
| 90 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); |
| 91 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); |
| 92 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); |
| 93 | } |
| 94 | |
| 95 | /* IO resource */ |
| 96 | acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, |
| 97 | ri->PciResourceIoLimit, 0x0, |
| 98 | (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); |
| 99 | |
| 100 | /* additional mem32 resources on socket 0 bus 0 */ |
| 101 | if (stack == 0) { |
| 102 | acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, |
| 103 | (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, |
| 104 | VGA_BASE_SIZE); |
| 105 | acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, |
| 106 | (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, |
| 107 | SPI_BASE_SIZE); |
| 108 | } |
| 109 | |
| 110 | /* Mem32 resource */ |
| 111 | acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, |
| 112 | ri->PciResourceMem32Limit, 0x0, |
| 113 | (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); |
| 114 | |
| 115 | /* Mem64 resource */ |
| 116 | acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, |
| 117 | ri->PciResourceMem64Limit, 0x0, |
| 118 | (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); |
| 119 | |
| 120 | acpigen_write_resourcetemplate_footer(); |
| 121 | } |
| 122 | acpigen_pop_len(); |
| 123 | } |
| 124 | |
| 125 | /* To be renamed soc_power_states_generation() */ |
| 126 | void cpx_generate_p_state_entries(int core, int cores_per_package) |
| 127 | { |
| 128 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 129 | int coord_type, power_max, power_unit, num_entries; |
| 130 | int ratio, power, clock, clock_max; |
| 131 | msr_t msr; |
| 132 | |
| 133 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 134 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 135 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 136 | coord_type = SW_ANY; |
| 137 | else |
| 138 | coord_type = HW_ALL; |
| 139 | |
| 140 | /* Get bus ratio limits and calculate clock speeds */ |
| 141 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 142 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 143 | |
| 144 | /* Determine if this CPU has configurable TDP */ |
| 145 | if (cpu_config_tdp_levels()) { |
| 146 | /* Set max ratio to nominal TDP ratio */ |
| 147 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 148 | ratio_max = msr.lo & 0xff; |
| 149 | } else { |
| 150 | /* Max Non-Turbo Ratio */ |
| 151 | ratio_max = (msr.lo >> 8) & 0xff; |
| 152 | } |
| 153 | clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; |
| 154 | |
| 155 | /* Calculate CPU TDP in mW */ |
| 156 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 157 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 158 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 159 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 160 | |
| 161 | /* Write _PCT indicating use of FFixedHW */ |
| 162 | acpigen_write_empty_PCT(); |
| 163 | |
| 164 | /* Write _PPC with no limit on supported P-state */ |
| 165 | acpigen_write_PPC_NVS(); |
| 166 | |
| 167 | /* Write PSD indicating configured coordination type */ |
| 168 | acpigen_write_PSD_package(core, 1, coord_type); |
| 169 | |
| 170 | /* Add P-state entries in _PSS table */ |
| 171 | acpigen_write_name("_PSS"); |
| 172 | |
| 173 | /* Determine ratio points */ |
| 174 | ratio_step = PSS_RATIO_STEP; |
| 175 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
| 176 | if (num_entries > PSS_MAX_ENTRIES) { |
| 177 | ratio_step += 1; |
| 178 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
| 179 | } |
| 180 | |
| 181 | /* P[T] is Turbo state if enabled */ |
| 182 | if (get_turbo_state() == TURBO_ENABLED) { |
| 183 | /* _PSS package count including Turbo */ |
| 184 | acpigen_write_package(num_entries + 2); |
| 185 | |
| 186 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 187 | ratio_turbo = msr.lo & 0xff; |
| 188 | |
| 189 | /* Add entry for Turbo ratio */ |
| 190 | acpigen_write_PSS_package( |
| 191 | clock_max + 1, /* MHz */ |
| 192 | power_max, /* mW */ |
| 193 | PSS_LATENCY_TRANSITION, /* lat1 */ |
| 194 | PSS_LATENCY_BUSMASTER, /* lat2 */ |
| 195 | ratio_turbo << 8, /* control */ |
| 196 | ratio_turbo << 8); /* status */ |
| 197 | } else { |
| 198 | /* _PSS package count without Turbo */ |
| 199 | acpigen_write_package(num_entries + 1); |
| 200 | } |
| 201 | |
| 202 | /* First regular entry is max non-turbo ratio */ |
| 203 | acpigen_write_PSS_package( |
| 204 | clock_max, /* MHz */ |
| 205 | power_max, /* mW */ |
| 206 | PSS_LATENCY_TRANSITION, /* lat1 */ |
| 207 | PSS_LATENCY_BUSMASTER, /* lat2 */ |
| 208 | ratio_max << 8, /* control */ |
| 209 | ratio_max << 8); /* status */ |
| 210 | |
| 211 | /* Generate the remaining entries */ |
| 212 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 213 | ratio >= ratio_min; ratio -= ratio_step) { |
| 214 | |
| 215 | /* Calculate power at this ratio */ |
| 216 | power = calculate_power(power_max, ratio_max, ratio); |
| 217 | clock = ratio * CONFIG_CPU_BCLK_MHZ; |
| 218 | //clock = 1; |
| 219 | acpigen_write_PSS_package( |
| 220 | clock, /* MHz */ |
| 221 | power, /* mW */ |
| 222 | PSS_LATENCY_TRANSITION, /* lat1 */ |
| 223 | PSS_LATENCY_BUSMASTER, /* lat2 */ |
| 224 | ratio << 8, /* control */ |
| 225 | ratio << 8); /* status */ |
| 226 | } |
| 227 | |
| 228 | /* Fix package length */ |
| 229 | acpigen_pop_len(); |
| 230 | } |
| 231 | |
| 232 | unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) |
| 233 | { |
| 234 | struct device *cpu; |
| 235 | uint8_t num_cpus = 0; |
| 236 | |
| 237 | for (cpu = all_devices; cpu; cpu = cpu->next) { |
| 238 | if ((cpu->path.type != DEVICE_PATH_APIC) || |
| 239 | (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { |
| 240 | continue; |
| 241 | } |
| 242 | if (!cpu->enabled) |
| 243 | continue; |
| 244 | current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, |
| 245 | num_cpus, cpu->path.apic.apic_id); |
| 246 | num_cpus++; |
| 247 | } |
| 248 | |
| 249 | return current; |
| 250 | } |
| 251 | |
| 252 | unsigned long acpi_create_srat_lapics(unsigned long current) |
| 253 | { |
| 254 | struct device *cpu; |
| 255 | unsigned int cpu_index = 0; |
| 256 | |
| 257 | for (cpu = all_devices; cpu; cpu = cpu->next) { |
| 258 | if ((cpu->path.type != DEVICE_PATH_APIC) || |
| 259 | (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { |
| 260 | continue; |
| 261 | } |
| 262 | if (!cpu->enabled) |
| 263 | continue; |
| 264 | printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", |
| 265 | cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); |
| 266 | current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, |
| 267 | cpu->path.apic.node_id, cpu->path.apic.apic_id); |
| 268 | cpu_index++; |
| 269 | } |
| 270 | return current; |
| 271 | } |
| 272 | |
| 273 | static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) |
| 274 | { |
| 275 | const struct SystemMemoryMapHob *memory_map; |
| 276 | unsigned int mmap_index; |
| 277 | |
| 278 | memory_map = get_system_memory_map(); |
| 279 | assert(memory_map != NULL); |
| 280 | printk(BIOS_DEBUG, "memory_map: %p\n", memory_map); |
| 281 | |
| 282 | mmap_index = 0; |
| 283 | for (int e = 0; e < memory_map->numberEntries; ++e) { |
| 284 | const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; |
| 285 | uint64_t addr = |
| 286 | (uint64_t) ((uint64_t)mem_element->BaseAddress << |
| 287 | MEM_ADDR_64MB_SHIFT_BITS); |
| 288 | uint64_t size = |
| 289 | (uint64_t) ((uint64_t)mem_element->ElementSize << |
| 290 | MEM_ADDR_64MB_SHIFT_BITS); |
| 291 | |
| 292 | printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " |
| 293 | "ElementSize: 0x%x, reserved: %d\n", |
| 294 | e, addr, mem_element->BaseAddress, size, |
| 295 | mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); |
| 296 | |
| 297 | assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); |
| 298 | |
| 299 | /* skip reserved memory region */ |
| 300 | if (mem_element->Type & MEM_TYPE_RESERVED) |
| 301 | continue; |
| 302 | |
| 303 | /* skip if this address is already added */ |
| 304 | bool skip = false; |
| 305 | for (int idx = 0; idx < mmap_index; ++idx) { |
| 306 | uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + |
| 307 | srat_mem[idx].base_address_low; |
| 308 | if (addr == base_addr) { |
| 309 | skip = true; |
| 310 | break; |
| 311 | } |
| 312 | } |
| 313 | if (skip) |
| 314 | continue; |
| 315 | |
| 316 | srat_mem[mmap_index].type = 1; /* Memory affinity structure */ |
| 317 | srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); |
| 318 | srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); |
| 319 | srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); |
| 320 | srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); |
| 321 | srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); |
| 322 | srat_mem[mmap_index].proximity_domain = mem_element->SocketId; |
| 323 | srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; |
| 324 | if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) |
| 325 | srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; |
| 326 | ++mmap_index; |
| 327 | } |
| 328 | |
| 329 | return mmap_index; |
| 330 | } |
| 331 | |
| 332 | static unsigned long acpi_fill_srat(unsigned long current) |
| 333 | { |
| 334 | acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; |
| 335 | unsigned int mem_count; |
| 336 | |
| 337 | /* create all subtables for processors */ |
| 338 | current = acpi_create_srat_lapics(current); |
| 339 | |
| 340 | mem_count = get_srat_memory_entries(srat_mem); |
| 341 | for (int i = 0; i < mem_count; ++i) { |
| 342 | printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " |
| 343 | "length: 0x%x%x, proximity_domain: %d, flags: %x\n", |
| 344 | i, srat_mem[i].length, |
| 345 | srat_mem[i].base_address_high, srat_mem[i].base_address_low, |
| 346 | srat_mem[i].length_high, srat_mem[i].length_low, |
| 347 | srat_mem[i].proximity_domain, srat_mem[i].flags); |
| 348 | memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); |
| 349 | current += srat_mem[i].length; |
| 350 | } |
| 351 | |
| 352 | return current; |
| 353 | } |
| 354 | |
| 355 | static unsigned long acpi_fill_slit(unsigned long current) |
| 356 | { |
| 357 | unsigned int nodes = xeon_sp_get_socket_count(); |
| 358 | |
| 359 | uint8_t *p = (uint8_t *)current; |
| 360 | memset(p, 0, 8 + nodes * nodes); |
| 361 | *p = (uint8_t)nodes; |
| 362 | p += 8; |
| 363 | |
| 364 | /* this assumes fully connected socket topology */ |
| 365 | for (int i = 0; i < nodes; i++) { |
| 366 | for (int j = 0; j < nodes; j++) { |
| 367 | if (i == j) |
| 368 | p[i*nodes+j] = 10; |
| 369 | else |
| 370 | p[i*nodes+j] = 16; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | current += 8 + nodes * nodes; |
| 375 | return current; |
| 376 | } |
| 377 | |
| 378 | /* |
| 379 | * Ports Stack Stack(HOB) IioConfigIou |
| 380 | * ========================================== |
| 381 | * 0 CSTACK stack 0 IOU0 |
| 382 | * 1A..1D PSTACK0 stack 1 IOU1 |
| 383 | * 2A..2D PSTACK1 stack 2 IOU2 |
| 384 | * 3A..3D PSTACK2 stack 4 IOU3 |
| 385 | */ |
| 386 | static int get_stack_for_port(int port) |
| 387 | { |
| 388 | if (port == PORT_0) |
| 389 | return CSTACK; |
| 390 | else if (port >= PORT_1A && port <= PORT_1D) |
| 391 | return PSTACK0; |
| 392 | else if (port >= PORT_2A && port <= PORT_2D) |
| 393 | return PSTACK1; |
| 394 | else if (port >= PORT_3A && port <= PORT_3D) |
| 395 | return PSTACK2; |
| 396 | else |
| 397 | return -1; |
| 398 | } |
| 399 | |
| 400 | /* |
| 401 | * This function adds PCIe bridge device entry in DMAR table. If it is called |
| 402 | * in the context of ATSR subtable, it adds ATSR subtable when it is first called. |
| 403 | */ |
| 404 | static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, |
| 405 | int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, |
| 406 | bool is_atsr, bool *first) |
| 407 | { |
| 408 | |
| 409 | if (get_stack_for_port(port) != stack) |
| 410 | return 0; |
| 411 | |
| 412 | const uint32_t bus = iio_resource.StackRes[stack].BusBase; |
| 413 | const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; |
| 414 | const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; |
| 415 | |
| 416 | const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), |
| 417 | PCI_VENDOR_ID); |
| 418 | if (id == 0xffffffff) |
| 419 | return 0; |
| 420 | |
| 421 | unsigned long atsr_size = 0; |
| 422 | unsigned long pci_br_size = 0; |
| 423 | if (is_atsr == true && first && *first == true) { |
| 424 | printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " |
| 425 | "PCI Segment Number: 0x%x\n", 0, pcie_seg); |
| 426 | atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); |
| 427 | *first = false; |
| 428 | } |
| 429 | |
| 430 | printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " |
| 431 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 432 | 0, bus, dev, func); |
| 433 | pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); |
| 434 | |
| 435 | return (atsr_size + pci_br_size); |
| 436 | } |
| 437 | |
| 438 | static unsigned long acpi_create_drhd(unsigned long current, int socket, |
| 439 | int stack, const IIO_UDS *hob) |
| 440 | { |
| 441 | int IoApicID[] = { |
| 442 | // socket 0 |
| 443 | PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, |
| 444 | PC04_IOAPIC_ID, PC05_IOAPIC_ID, |
| 445 | // socket 1 |
| 446 | PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, |
| 447 | PC10_IOAPIC_ID, PC11_IOAPIC_ID, |
| 448 | }; |
| 449 | |
| 450 | uint32_t enum_id; |
| 451 | unsigned long tmp = current; |
| 452 | |
| 453 | uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; |
| 454 | uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; |
| 455 | uint32_t reg_base = |
| 456 | hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; |
| 457 | printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", |
| 458 | __func__, socket, stack, bus, pcie_seg, reg_base); |
| 459 | |
| 460 | // Add DRHD Hardware Unit |
| 461 | if (socket == 0 && stack == CSTACK) { |
| 462 | printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " |
| 463 | "Register Base Address: 0x%x\n", |
| 464 | DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); |
| 465 | current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, |
| 466 | pcie_seg, reg_base); |
| 467 | } else { |
| 468 | printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " |
| 469 | "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); |
| 470 | current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); |
| 471 | } |
| 472 | |
| 473 | // Add PCH IOAPIC |
| 474 | if (socket == 0 && stack == CSTACK) { |
| 475 | printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 476 | "PCI Path: 0x%x, 0x%x\n", |
| 477 | PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, |
| 478 | PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); |
| 479 | current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, |
| 480 | PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); |
| 481 | } |
| 482 | |
| 483 | // Add IOAPIC entry |
| 484 | enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; |
| 485 | printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 486 | "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); |
| 487 | current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, |
| 488 | APIC_DEV_NUM, APIC_FUNC_NUM); |
| 489 | |
| 490 | // Add CBDMA devices for CSTACK |
| 491 | if (socket != 0 && stack == CSTACK) { |
| 492 | for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { |
| 493 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " |
| 494 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 495 | 0, bus, CBDMA_DEV_NUM, cbdma_func_id); |
| 496 | current += acpi_create_dmar_ds_pci(current, |
| 497 | bus, CBDMA_DEV_NUM, cbdma_func_id); |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | // Add PCIe Ports |
| 502 | if (socket != 0 || stack != CSTACK) { |
| 503 | IIO_RESOURCE_INSTANCE iio_resource = |
| 504 | hob->PlatformData.IIO_resource[socket]; |
| 505 | for (int p = PORT_0; p < MAX_PORTS; ++p) |
| 506 | current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, |
| 507 | iio_resource, pcie_seg, false, NULL); |
| 508 | |
| 509 | // Add VMD |
| 510 | if (hob->PlatformData.VMDStackEnable[socket][stack] && |
| 511 | stack >= PSTACK0 && stack <= PSTACK2) { |
| 512 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " |
| 513 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 514 | 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); |
| 515 | current += acpi_create_dmar_ds_pci(current, |
| 516 | bus, VMD_DEV_NUM, VMD_FUNC_NUM); |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | // Add HPET |
| 521 | if (socket == 0 && stack == CSTACK) { |
| 522 | uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); |
| 523 | uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count |
| 524 | printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", |
| 525 | __func__, hpet_capid, num_hpets); |
| 526 | //BIT 15 |
| 527 | if (num_hpets && (num_hpets != 0x1f) && |
| 528 | (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { |
| 529 | printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " |
| 530 | "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", |
| 531 | 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); |
| 532 | current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, |
| 533 | HPET_DEV_NUM, HPET0_FUNC_NUM); |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | acpi_dmar_drhd_fixup(tmp, current); |
| 538 | |
| 539 | return current; |
| 540 | } |
| 541 | |
| 542 | static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) |
| 543 | { |
| 544 | for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { |
| 545 | uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; |
| 546 | unsigned long tmp = current; |
| 547 | bool first = true; |
| 548 | IIO_RESOURCE_INSTANCE iio_resource = |
| 549 | hob->PlatformData.IIO_resource[socket]; |
| 550 | |
| 551 | for (int stack = 0; stack <= PSTACK2; ++stack) { |
| 552 | uint32_t bus = iio_resource.StackRes[stack].BusBase; |
| 553 | uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; |
| 554 | if (!vtd_base) |
| 555 | continue; |
| 556 | uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); |
| 557 | printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " |
| 558 | "vtd_mmio_cap: 0x%llx\n", |
| 559 | __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); |
| 560 | |
| 561 | // ATSR is applicable only for platform supporting device IOTLBs |
| 562 | // through the VT-d extended capability register |
| 563 | assert(vtd_mmio_cap != 0xffffffffffffffff); |
| 564 | if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 |
| 565 | continue; |
| 566 | |
| 567 | for (int p = PORT_0; p < MAX_PORTS; ++p) { |
| 568 | if (socket == 0 && p == PORT_0) |
| 569 | continue; |
| 570 | current += acpi_create_dmar_ds_pci_br_for_port(current, p, |
| 571 | stack, iio_resource, pcie_seg, true, &first); |
| 572 | } |
| 573 | } |
| 574 | if (tmp != current) |
| 575 | acpi_dmar_atsr_fixup(tmp, current); |
| 576 | } |
| 577 | |
| 578 | return current; |
| 579 | } |
| 580 | |
| 581 | static unsigned long acpi_create_rmrr(unsigned long current) |
| 582 | { |
| 583 | uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); |
| 584 | |
| 585 | uint32_t *ptr; |
| 586 | |
| 587 | // reserve memory |
| 588 | ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); |
| 589 | if (!ptr) { |
| 590 | ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); |
| 591 | assert(ptr != NULL); |
| 592 | memset(ptr, 0, size); |
| 593 | } |
| 594 | |
| 595 | unsigned long tmp = current; |
| 596 | printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " |
| 597 | "End Address (limit): 0x%x\n", |
| 598 | 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); |
| 599 | current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, |
| 600 | (uint32_t) ((uint32_t) ptr + size - 1)); |
| 601 | |
| 602 | printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " |
| 603 | "PCI Path: 0x%x, 0x%x\n", |
| 604 | 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); |
| 605 | current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, |
| 606 | PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); |
| 607 | |
| 608 | acpi_dmar_rmrr_fixup(tmp, current); |
| 609 | |
| 610 | return current; |
| 611 | } |
| 612 | |
| 613 | static unsigned long acpi_create_rhsa(unsigned long current) |
| 614 | { |
| 615 | size_t hob_size; |
| 616 | const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; |
| 617 | const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); |
| 618 | assert(hob != NULL && hob_size != 0); |
| 619 | |
| 620 | for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { |
| 621 | IIO_RESOURCE_INSTANCE iio_resource = |
| 622 | hob->PlatformData.IIO_resource[socket]; |
| 623 | for (int stack = 0; stack <= PSTACK2; ++stack) { |
| 624 | uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; |
| 625 | if (!vtd_base) |
| 626 | continue; |
| 627 | |
| 628 | printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " |
| 629 | "Proximity Domain: 0x%x\n", vtd_base, socket); |
| 630 | current += acpi_create_dmar_rhsa(current, vtd_base, socket); |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | return current; |
| 635 | } |
| 636 | |
| 637 | static unsigned long acpi_fill_dmar(unsigned long current) |
| 638 | { |
| 639 | size_t hob_size; |
| 640 | const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; |
| 641 | const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); |
| 642 | assert(hob != NULL && hob_size != 0); |
| 643 | |
| 644 | // DRHD |
| 645 | for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { |
| 646 | int socket = iio; |
| 647 | if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry |
| 648 | socket = 0; |
| 649 | |
| 650 | if (socket == 0) { |
| 651 | for (int stack = 1; stack <= PSTACK2; ++stack) |
| 652 | current = acpi_create_drhd(current, socket, stack, hob); |
| 653 | current = acpi_create_drhd(current, socket, CSTACK, hob); |
| 654 | } else { |
| 655 | for (int stack = 0; stack <= PSTACK2; ++stack) |
| 656 | current = acpi_create_drhd(current, socket, stack, hob); |
| 657 | } |
| 658 | } |
| 659 | |
| 660 | // RMRR |
| 661 | current = acpi_create_rmrr(current); |
| 662 | |
| 663 | // Root Port ATS Capability |
| 664 | current = acpi_create_atsr(current, hob); |
| 665 | |
| 666 | // RHSA |
| 667 | current = acpi_create_rhsa(current); |
| 668 | |
| 669 | return current; |
| 670 | } |
| 671 | |
| 672 | unsigned long northbridge_write_acpi_tables(const struct device *device, |
| 673 | unsigned long current, |
| 674 | struct acpi_rsdp *rsdp) |
| 675 | { |
| 676 | acpi_srat_t *srat; |
| 677 | acpi_slit_t *slit; |
| 678 | acpi_dmar_t *dmar; |
| 679 | |
| 680 | const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device); |
| 681 | |
| 682 | /* SRAT */ |
| 683 | current = ALIGN(current, 8); |
| 684 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 685 | srat = (acpi_srat_t *) current; |
| 686 | acpi_create_srat(srat, acpi_fill_srat); |
| 687 | current += srat->header.length; |
| 688 | acpi_add_table(rsdp, srat); |
| 689 | |
| 690 | /* SLIT */ |
| 691 | current = ALIGN(current, 8); |
| 692 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 693 | slit = (acpi_slit_t *) current; |
| 694 | acpi_create_slit(slit, acpi_fill_slit); |
| 695 | current += slit->header.length; |
| 696 | acpi_add_table(rsdp, slit); |
| 697 | |
| 698 | /* DMAR */ |
| 699 | if (config->vtd_support) { |
| 700 | current = ALIGN(current, 8); |
| 701 | dmar = (acpi_dmar_t *)current; |
| 702 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 703 | printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); |
| 704 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); |
| 705 | current += dmar->header.length; |
| 706 | current = acpi_align_current(current); |
| 707 | acpi_add_table(rsdp, dmar); |
| 708 | } |
| 709 | |
| 710 | return current; |
| 711 | } |