blob: 05003a210d1144c8c5138c14bca10494b742695f [file] [log] [blame]
jinkun.hongac490b82014-06-22 20:40:39 -07001##
2## This file is part of the coreboot project.
3##
4## Copyright 2014 Rockchip Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
17## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18##
19
20#bootblock-y += bootblock.c
21bootblock-y += cbmem.c
22bootblock-y += timer.c
23bootblock-y += monotonic_timer.c
24bootblock-y += media.c
25ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
26bootblock-$(CONFIG_DRIVERS_UART) += uart.c
27endif
jinkun.hong503d1212014-07-31 14:50:49 +080028bootblock-y += clock.c
huang lin630c86d2014-08-26 17:28:46 +080029bootblock-y += spi.c
jinkun.hongac490b82014-06-22 20:40:39 -070030
31romstage-y += cbmem.c
32romstage-y += timer.c
33romstage-y += monotonic_timer.c
34romstage-y += media.c
35romstage-$(CONFIG_DRIVERS_UART) += uart.c
jinkun.hong503d1212014-07-31 14:50:49 +080036romstage-y += clock.c
huang lin630c86d2014-08-26 17:28:46 +080037romstage-y += spi.c
jinkun.hongac490b82014-06-22 20:40:39 -070038
39ramstage-y += cbmem.c
40ramstage-y += timer.c
41ramstage-y += monotonic_timer.c
jinkun.hong503d1212014-07-31 14:50:49 +080042ramstage-y += clock.c
huang lin630c86d2014-08-26 17:28:46 +080043ramstage-y += spi.c
jinkun.hongac490b82014-06-22 20:40:39 -070044ramstage-y += media.c
45ramstage-$(CONFIG_DRIVERS_UART) += uart.c