rk3288: add spi
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I858ac723d640dde8538aebb968fcff364fa7207c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8253a9dbad2afdf9eb9a8554fd355e6815887407
Original-Change-Id: Ib6ee7e3092429a3e47b102751ed6a88aeb9ee7d3
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209429
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8859
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index 13c8114..05003a2 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -26,6 +26,7 @@
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
bootblock-y += clock.c
+bootblock-y += spi.c
romstage-y += cbmem.c
romstage-y += timer.c
@@ -33,10 +34,12 @@
romstage-y += media.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += clock.c
+romstage-y += spi.c
ramstage-y += cbmem.c
ramstage-y += timer.c
ramstage-y += monotonic_timer.c
ramstage-y += clock.c
+ramstage-y += spi.c
ramstage-y += media.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c