Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
| 19 | #include <string.h> |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <lib.h> |
| 23 | #include <cpu/x86/lapic.h> |
| 24 | #include <timestamp.h> |
| 25 | #include "sandybridge.h" |
| 26 | #include <cpu/x86/bist.h> |
| 27 | #include <cpu/intel/romstage.h> |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 28 | #include <device/pci_def.h> |
| 29 | #include <device/device.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 30 | #include <halt.h> |
Vladimir Serbinenko | ed54cc7 | 2015-05-18 10:31:35 +0200 | [diff] [blame] | 31 | #include <tpm.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 32 | #include "raminit_native.h" |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 33 | #include <northbridge/intel/sandybridge/chip.h> |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 34 | #include "southbridge/intel/bd82x6x/pch.h" |
| 35 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 36 | |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 37 | #define HOST_BRIDGE PCI_DEVFN(0, 0) |
| 38 | #define DEFAULT_TCK TCK_800MHZ |
| 39 | |
| 40 | static unsigned int get_mem_min_tck(void) |
| 41 | { |
| 42 | const struct device *dev; |
| 43 | const struct northbridge_intel_sandybridge_config *cfg; |
| 44 | |
| 45 | dev = dev_find_slot(0, HOST_BRIDGE); |
| 46 | if (!(dev && dev->chip_info)) |
| 47 | return DEFAULT_TCK; |
| 48 | |
| 49 | cfg = dev->chip_info; |
| 50 | |
| 51 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 52 | if (cfg->max_mem_clock_mhz == 0) |
| 53 | return DEFAULT_TCK; |
| 54 | |
| 55 | if (cfg->max_mem_clock_mhz >= 800) |
| 56 | return TCK_800MHZ; |
| 57 | else if (cfg->max_mem_clock_mhz >= 666) |
| 58 | return TCK_666MHZ; |
| 59 | else if (cfg->max_mem_clock_mhz >= 533) |
| 60 | return TCK_533MHZ; |
| 61 | else |
| 62 | return TCK_400MHZ; |
| 63 | } |
| 64 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 65 | void main(unsigned long bist) |
| 66 | { |
| 67 | int s3resume = 0; |
| 68 | spd_raw_data spd[4]; |
| 69 | |
| 70 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 71 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 72 | halt (); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | timestamp_init(get_initial_timestamp()); |
| 76 | timestamp_add_now(TS_START_ROMSTAGE); |
| 77 | |
| 78 | if (bist == 0) |
| 79 | enable_lapic(); |
| 80 | |
| 81 | pch_enable_lpc(); |
| 82 | |
| 83 | /* Enable GPIOs */ |
| 84 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 85 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 86 | |
| 87 | setup_pch_gpios(&mainboard_gpio_map); |
| 88 | |
| 89 | early_usb_init(mainboard_usb_ports); |
| 90 | |
| 91 | /* Initialize console device(s) */ |
| 92 | console_init(); |
| 93 | |
| 94 | /* Halt if there was a built in self test failure */ |
| 95 | report_bist_failure(bist); |
| 96 | |
| 97 | /* Perform some early chipset initialization required |
| 98 | * before RAM initialization can work |
| 99 | */ |
| 100 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 101 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 102 | |
| 103 | s3resume = southbridge_detect_s3_resume(); |
| 104 | |
| 105 | post_code(0x38); |
Vladimir Serbinenko | 609bd94 | 2016-01-31 14:00:54 +0100 | [diff] [blame] | 106 | |
| 107 | mainboard_early_init(s3resume); |
| 108 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 109 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 110 | enable_smbus(); |
| 111 | |
| 112 | post_code(0x39); |
| 113 | |
| 114 | post_code(0x3a); |
| 115 | |
| 116 | memset (spd, 0, sizeof (spd)); |
| 117 | mainboard_get_spd(spd); |
| 118 | |
| 119 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 120 | |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 121 | init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 122 | |
| 123 | timestamp_add_now(TS_AFTER_INITRAM); |
| 124 | post_code(0x3c); |
| 125 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 126 | southbridge_configure_default_intmap(); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 127 | rcba_config(); |
| 128 | post_code(0x3d); |
| 129 | |
| 130 | northbridge_romstage_finalize(s3resume); |
| 131 | |
Vladimir Serbinenko | ed54cc7 | 2015-05-18 10:31:35 +0200 | [diff] [blame] | 132 | #if CONFIG_LPC_TPM |
| 133 | init_tpm(s3resume); |
| 134 | #endif |
| 135 | |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 136 | post_code(0x3f); |
Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 137 | } |