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review.coreboot.org / coreboot / 622eea7e815af39dbee290eddc487baab5e8a5f5 / src / northbridge / intel / sandybridge / romstage.c
  1. 609bd94 ivy: Add a possiblity for mainboard early init. by Vladimir Serbinenko · 9 years ago
  2. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  3. ecf2eb4 sandybridge ivybridge: Treat native init as first class citizen by Alexandru Gagniuc · 9 years ago[Renamed from src/northbridge/intel/sandybridge/romstage_native.c]
  4. 9796f60 coreboot: move TS_END_ROMSTAGE to one spot by Aaron Durbin · 9 years ago
  5. ed54cc7 sandybridge native: Add call to TPM code. by Vladimir Serbinenko · 9 years ago
  6. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  7. 8b2c8f1 sandybridge/raminit: Get max mem clock from devicetree by Alexandru Gagniuc · 10 years ago
  8. bd79c5e Replace hlt() loops with halt() by Patrick Georgi · 10 years ago
  9. 33b535f sandy/ivy/nehalem: Remerge interrupt handling by Vladimir Serbinenko · 10 years ago
  10. fa1d688 sandy/ivy native: dedup romstage.c main() by Vladimir Serbinenko · 10 years ago