Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 2 | |
| 3 | #include <arch/io.h> |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 4 | #include <console/post_codes.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Patrick Rudolph | 2dc6389 | 2018-06-28 14:13:06 +0200 | [diff] [blame] | 6 | #include <southbridge/intel/common/pmbase.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 7 | #include <southbridge/intel/common/pmutil.h> |
| 8 | #include <southbridge/intel/common/rcba.h> |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 9 | #include <spi-generic.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 10 | |
| 11 | #include "finalize.h" |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 12 | |
| 13 | void intel_pch_finalize_smm(void) |
| 14 | { |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 15 | const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); |
| 16 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 17 | /* Lock SPIBAR */ |
| 18 | RCBA32_OR(0x3804, (1 << 15)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 19 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 20 | if (CONFIG(SPI_FLASH_SMM)) |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 21 | /* Re-init SPI driver to handle locked BAR */ |
| 22 | spi_init(); |
Duncan Laurie | 312ee0c | 2012-09-09 20:12:32 -0700 | [diff] [blame] | 23 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 24 | /* TCLOCKDN: TC Lockdown */ |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 25 | RCBA32_OR(0x0050, (1UL << 31)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 26 | |
| 27 | /* BIOS Interface Lockdown */ |
| 28 | RCBA32_OR(0x3410, (1 << 0)); |
| 29 | |
| 30 | /* Function Disable SUS Well Lockdown */ |
| 31 | RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); |
| 32 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 33 | pci_or_config16(lpc_dev, D31F0_GEN_PMCON_1, SMI_LOCK); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 34 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 35 | pci_or_config8(lpc_dev, D31F0_GEN_PMCON_LOCK, |
| 36 | ACPI_BASE_LOCK | SLP_STR_POL_LOCK); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 37 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 38 | pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); |
| 39 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 40 | if (CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)) |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 41 | /* PMSYNC */ |
| 42 | RCBA32_OR(0x33c4, (1UL << 31)); |
Patrick Rudolph | 7565cf1 | 2017-05-03 18:38:21 +0200 | [diff] [blame] | 43 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 44 | /* R/WO registers */ |
| 45 | RCBA32(0x21a4) = RCBA32(0x21a4); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 46 | pci_write_config32(PCI_DEV(0, 27, 0), 0x74, |
| 47 | pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 48 | |
Patrick Rudolph | 2dc6389 | 2018-06-28 14:13:06 +0200 | [diff] [blame] | 49 | write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK); |
Dennis Wassenberg | 0c04720 | 2015-09-10 12:03:45 +0200 | [diff] [blame] | 50 | |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 51 | outb(POST_OS_BOOT, CONFIG_POST_IO_PORT); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 52 | } |