Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 21 | #include <arch/io.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 22 | #include <device/pci.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <device/pnp_def.h> |
| 25 | #include <cpu/x86/lapic.h> |
| 26 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 27 | #include <arch/acpi.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 28 | #include <cbmem.h> |
| 29 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 30 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 31 | #include <northbridge/intel/sandybridge/raminit.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <southbridge/intel/bd82x6x/gpio.h> |
Vladimir Serbinenko | 613d3ad | 2016-02-10 01:43:08 +0100 | [diff] [blame^] | 33 | #include <southbridge/intel/bd82x6x/pch.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 34 | #include "ec/google/chromeec/ec.h" |
| 35 | #include <arch/cpu.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 36 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 37 | #include <halt.h> |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 38 | #include <tpm.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 39 | #include <cbfs.h> |
| 40 | |
| 41 | #include <southbridge/intel/bd82x6x/chip.h> |
| 42 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 43 | void pch_enable_lpc(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 44 | { |
| 45 | const struct device *lpc; |
| 46 | const struct southbridge_intel_bd82x6x_config *config = NULL; |
| 47 | |
| 48 | lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); |
| 49 | if (!lpc) |
| 50 | return; |
| 51 | if (lpc->chip_info) |
| 52 | config = lpc->chip_info; |
| 53 | if (!config) |
| 54 | return; |
| 55 | |
| 56 | /* Set COM1/COM2 decode range */ |
| 57 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 58 | |
| 59 | /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ |
| 60 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ |
| 61 | GAMEL_LPC_EN | COMA_LPC_EN); |
| 62 | |
| 63 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); |
| 64 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); |
| 65 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); |
| 66 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); |
| 67 | } |
| 68 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 69 | void rcba_config(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 70 | { |
| 71 | u32 reg32; |
| 72 | |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 73 | /* |
| 74 | * GFX INTA -> PIRQA (MSI) |
| 75 | * D28IP_P3IP WLAN INTA -> PIRQB |
| 76 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 77 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 78 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 79 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 80 | * D31IP_TTIP THRT INTC -> PIRQA |
| 81 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 82 | * |
| 83 | * TRACKPAD -> PIRQE (Edge Triggered) |
| 84 | * TOUCHSCREEN -> PIRQG (Edge Triggered) |
| 85 | */ |
| 86 | |
| 87 | /* Device interrupt pin register (board specific) */ |
| 88 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 89 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 90 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 91 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 92 | RCBA32(D28IP) = (INTA << D28IP_P3IP); |
| 93 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 94 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 95 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 96 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 97 | |
| 98 | /* Device interrupt route registers */ |
| 99 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 100 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 101 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 102 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 103 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 104 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 105 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 106 | |
| 107 | /* Enable IOAPIC (generic) */ |
| 108 | RCBA16(OIC) = 0x0100; |
| 109 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 110 | (void) RCBA16(OIC); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 111 | |
| 112 | /* Disable unused devices (board specific) */ |
| 113 | reg32 = RCBA32(FD); |
| 114 | reg32 |= PCH_DISABLE_ALWAYS; |
| 115 | RCBA32(FD) = reg32; |
| 116 | } |
| 117 | |
| 118 | static void copy_spd(struct pei_data *peid) |
| 119 | { |
| 120 | const int gpio_vector[] = {41, 42, 43, 10, -1}; |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 121 | char *spd_file; |
| 122 | size_t spd_file_len; |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 123 | int spd_index = get_gpios(gpio_vector); |
| 124 | |
| 125 | printk(BIOS_DEBUG, "spd index %d\n", spd_index); |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 126 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 127 | &spd_file_len); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 128 | if (!spd_file) |
| 129 | die("SPD data not found."); |
| 130 | |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 131 | if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 132 | printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); |
| 133 | spd_index = 0; |
| 134 | } |
| 135 | |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 136 | if (spd_file_len < sizeof(peid->spd_data[0])) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 137 | die("Missing SPD data."); |
| 138 | |
| 139 | memcpy(peid->spd_data[0], |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 140 | spd_file + |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 141 | spd_index * sizeof(peid->spd_data[0]), |
| 142 | sizeof(peid->spd_data[0])); |
| 143 | } |
| 144 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 145 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 146 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 147 | struct pei_data pei_data_template = { |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 148 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 149 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 150 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 151 | .epbar = DEFAULT_EPBAR, |
| 152 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 153 | .smbusbar = SMBUS_IO_BASE, |
| 154 | .wdbbar = 0x4000000, |
| 155 | .wdbsize = 0x1000, |
| 156 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 157 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 158 | .pmbase = DEFAULT_PMBASE, |
| 159 | .gpiobase = DEFAULT_GPIOBASE, |
| 160 | .thermalbase = 0xfed08000, |
| 161 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 162 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 163 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 164 | .ec_present = 1, |
| 165 | .ddr3lv_support = 1, |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 166 | // 0 = leave channel enabled |
| 167 | // 1 = disable dimm 0 on channel |
| 168 | // 2 = disable dimm 1 on channel |
| 169 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 170 | .dimm_channel0_disabled = 2, |
| 171 | .dimm_channel1_disabled = 2, |
| 172 | .max_ddr3_freq = 1600, |
| 173 | .usb_port_config = { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 174 | /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ |
| 175 | { 0, 3, 0x0000 }, /* P0: Empty */ |
| 176 | { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ |
| 177 | { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ |
| 178 | { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ |
| 179 | { 0, 3, 0x0000 }, /* P4: Empty */ |
| 180 | { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ |
| 181 | { 0, 3, 0x0000 }, /* P6: Empty */ |
| 182 | { 0, 3, 0x0000 }, /* P7: Empty */ |
| 183 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 184 | { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ |
| 185 | { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ |
| 186 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 187 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 188 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 189 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 190 | }, |
| 191 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 192 | *pei_data = pei_data_template; |
| 193 | copy_spd(pei_data); |
| 194 | } |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 195 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 196 | void mainboard_early_init(int s3resume) |
| 197 | { |
| 198 | if (!s3resume) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 199 | /* This is the fastest way to let users know |
| 200 | * the Intel CPU is now alive. |
| 201 | */ |
| 202 | google_chromeec_kbbacklight(100); |
| 203 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 204 | } |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 205 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 206 | int mainboard_should_reset_usb(int s3resume) |
| 207 | { |
| 208 | return !s3resume; |
| 209 | } |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 210 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 211 | void mainboard_config_superio(void) |
| 212 | { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 213 | } |