Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 25 | #include <arch/io.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 26 | #include <device/pci.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 31 | #include <arch/acpi.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 32 | #include <cbmem.h> |
| 33 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 34 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 35 | #include <northbridge/intel/sandybridge/raminit.h> |
| 36 | #include <southbridge/intel/bd82x6x/pch.h> |
| 37 | #include <southbridge/intel/bd82x6x/gpio.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 38 | #include "ec/google/chromeec/ec.h" |
| 39 | #include <arch/cpu.h> |
| 40 | #include <cpu/x86/bist.h> |
| 41 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 42 | #include <halt.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 43 | #include "gpio.h" |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 44 | #include <tpm.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 45 | #include <cbfs.h> |
| 46 | |
| 47 | #include <southbridge/intel/bd82x6x/chip.h> |
| 48 | |
| 49 | static void pch_enable_lpc(void) |
| 50 | { |
| 51 | const struct device *lpc; |
| 52 | const struct southbridge_intel_bd82x6x_config *config = NULL; |
| 53 | |
| 54 | lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); |
| 55 | if (!lpc) |
| 56 | return; |
| 57 | if (lpc->chip_info) |
| 58 | config = lpc->chip_info; |
| 59 | if (!config) |
| 60 | return; |
| 61 | |
| 62 | /* Set COM1/COM2 decode range */ |
| 63 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 64 | |
| 65 | /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ |
| 66 | pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ |
| 67 | GAMEL_LPC_EN | COMA_LPC_EN); |
| 68 | |
| 69 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); |
| 70 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); |
| 71 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); |
| 72 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); |
| 73 | } |
| 74 | |
| 75 | static void rcba_config(void) |
| 76 | { |
| 77 | u32 reg32; |
| 78 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 79 | southbridge_configure_default_intmap(); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 80 | |
| 81 | /* Disable unused devices (board specific) */ |
| 82 | reg32 = RCBA32(FD); |
| 83 | reg32 |= PCH_DISABLE_ALWAYS; |
| 84 | RCBA32(FD) = reg32; |
| 85 | } |
| 86 | |
| 87 | static void copy_spd(struct pei_data *peid) |
| 88 | { |
| 89 | const int gpio_vector[] = {41, 42, 43, 10, -1}; |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 90 | char *spd_file; |
| 91 | size_t spd_file_len; |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 92 | int spd_index = get_gpios(gpio_vector); |
| 93 | |
| 94 | printk(BIOS_DEBUG, "spd index %d\n", spd_index); |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame^] | 95 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 96 | &spd_file_len); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 97 | if (!spd_file) |
| 98 | die("SPD data not found."); |
| 99 | |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 100 | if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 101 | printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); |
| 102 | spd_index = 0; |
| 103 | } |
| 104 | |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 105 | if (spd_file_len < sizeof(peid->spd_data[0])) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 106 | die("Missing SPD data."); |
| 107 | |
| 108 | memcpy(peid->spd_data[0], |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 109 | spd_file + |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 110 | spd_index * sizeof(peid->spd_data[0]), |
| 111 | sizeof(peid->spd_data[0])); |
| 112 | } |
| 113 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 114 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 115 | void main(unsigned long bist) |
| 116 | { |
| 117 | int boot_mode = 0; |
| 118 | int cbmem_was_initted; |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 119 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 120 | struct pei_data pei_data = { |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 121 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 122 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 123 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 124 | .epbar = DEFAULT_EPBAR, |
| 125 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 126 | .smbusbar = SMBUS_IO_BASE, |
| 127 | .wdbbar = 0x4000000, |
| 128 | .wdbsize = 0x1000, |
| 129 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 130 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 131 | .pmbase = DEFAULT_PMBASE, |
| 132 | .gpiobase = DEFAULT_GPIOBASE, |
| 133 | .thermalbase = 0xfed08000, |
| 134 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 135 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 136 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 137 | .ec_present = 1, |
| 138 | .ddr3lv_support = 1, |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 139 | // 0 = leave channel enabled |
| 140 | // 1 = disable dimm 0 on channel |
| 141 | // 2 = disable dimm 1 on channel |
| 142 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | 6cec824 | 2014-05-24 04:16:57 +1000 | [diff] [blame] | 143 | .dimm_channel0_disabled = 2, |
| 144 | .dimm_channel1_disabled = 2, |
| 145 | .max_ddr3_freq = 1600, |
| 146 | .usb_port_config = { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 147 | /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ |
| 148 | { 0, 3, 0x0000 }, /* P0: Empty */ |
| 149 | { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ |
| 150 | { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ |
| 151 | { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ |
| 152 | { 0, 3, 0x0000 }, /* P4: Empty */ |
| 153 | { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ |
| 154 | { 0, 3, 0x0000 }, /* P6: Empty */ |
| 155 | { 0, 3, 0x0000 }, /* P7: Empty */ |
| 156 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 157 | { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ |
| 158 | { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ |
| 159 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 160 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 161 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 162 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 163 | }, |
| 164 | }; |
| 165 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 166 | timestamp_init(get_initial_timestamp()); |
| 167 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 168 | |
| 169 | if (bist == 0) |
| 170 | enable_lapic(); |
| 171 | |
| 172 | pch_enable_lpc(); |
| 173 | |
| 174 | /* Enable GPIOs */ |
| 175 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 176 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 177 | setup_pch_gpios(&link_gpio_map); |
| 178 | |
| 179 | /* Initialize console device(s) */ |
| 180 | console_init(); |
| 181 | |
| 182 | /* Halt if there was a built in self test failure */ |
| 183 | report_bist_failure(bist); |
| 184 | |
| 185 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 186 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 187 | boot_mode = 1; |
| 188 | |
| 189 | /* System is not happy after keyboard reset... */ |
| 190 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 191 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 192 | halt(); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | /* Perform some early chipset initialization required |
| 196 | * before RAM initialization can work |
| 197 | */ |
| 198 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 199 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 200 | |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 201 | boot_mode = southbridge_detect_s3_resume() ? 2 : 0; |
| 202 | if (boot_mode == 0) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 203 | /* This is the fastest way to let users know |
| 204 | * the Intel CPU is now alive. |
| 205 | */ |
| 206 | google_chromeec_kbbacklight(100); |
| 207 | } |
| 208 | |
| 209 | post_code(0x38); |
| 210 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 211 | enable_smbus(); |
| 212 | |
| 213 | /* Prepare USB controller early in S3 resume */ |
| 214 | if (boot_mode == 2) |
| 215 | enable_usb_bar(); |
| 216 | |
| 217 | post_code(0x39); |
| 218 | |
| 219 | copy_spd(&pei_data); |
| 220 | |
| 221 | post_code(0x3a); |
| 222 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 223 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 224 | sdram_initialize(&pei_data); |
| 225 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 226 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 227 | post_code(0x3c); |
| 228 | |
| 229 | rcba_config(); |
| 230 | post_code(0x3d); |
| 231 | |
| 232 | quick_ram_check(); |
| 233 | post_code(0x3e); |
| 234 | |
Kyösti Mälkki | 2d8520b | 2014-01-06 17:20:31 +0200 | [diff] [blame] | 235 | cbmem_was_initted = !cbmem_recovery(boot_mode==2); |
Kyösti Mälkki | 7893848 | 2014-01-04 11:02:45 +0200 | [diff] [blame] | 236 | if (boot_mode!=2) |
| 237 | save_mrc_data(&pei_data); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 238 | |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 239 | if (boot_mode==2 && !cbmem_was_initted) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 240 | /* Failed S3 resume, reset to come up cleanly */ |
| 241 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 242 | halt(); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 243 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 244 | northbridge_romstage_finalize(boot_mode==2); |
| 245 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 246 | post_code(0x3f); |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 247 | if (CONFIG_LPC_TPM) { |
| 248 | init_tpm(boot_mode == 2); |
| 249 | } |
| 250 | |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 251 | timestamp_add_now(TS_END_ROMSTAGE); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 252 | } |