Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | config SOC_INTEL_SKYLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Skylake support |
| 5 | |
| 6 | if SOC_INTEL_SKYLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Aaron Durbin | e0a4914 | 2016-07-13 23:20:51 -0500 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 11 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 12 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 15 | select ACPI_NHLT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 16 | select CACHE_MRC_SETTINGS |
Alexandru Gagniuc | 27fea06 | 2015-08-29 20:00:24 -0700 | [diff] [blame] | 17 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 18 | select COLLECT_TIMESTAMPS |
| 19 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Aaron Durbin | ffdf901 | 2015-07-24 13:00:36 -0500 | [diff] [blame] | 20 | select GENERIC_GPIO_LIB |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 21 | select HAVE_HARD_RESET |
Aaron Durbin | 387084c | 2015-07-30 13:41:01 -0500 | [diff] [blame] | 22 | select HAVE_INTEL_FIRMWARE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 23 | select HAVE_MONOTONIC_TIMER |
| 24 | select HAVE_SMI_HANDLER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 25 | select IOAPIC |
| 26 | select MMCONF_SUPPORT |
| 27 | select MMCONF_SUPPORT_DEFAULT |
Aaron Durbin | f5ff854 | 2016-05-05 10:38:03 -0500 | [diff] [blame] | 28 | select NO_FIXED_XIP_ROM_SIZE |
Duncan Laurie | 205ed2d | 2016-06-02 15:23:42 -0700 | [diff] [blame] | 29 | select MRC_SETTINGS_PROTECT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 30 | select PARALLEL_MP |
| 31 | select PCIEXP_ASPM |
| 32 | select PCIEXP_COMMON_CLOCK |
| 33 | select PCIEXP_CLK_PM |
Aaron Durbin | 27d153c | 2015-07-13 13:50:34 -0500 | [diff] [blame] | 34 | select PCIEXP_L1_SUB_STATE |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 35 | select PLATFORM_USES_FSP1_1 |
| 36 | select REG_SCRIPT |
| 37 | select RELOCATABLE_MODULES |
| 38 | select RELOCATABLE_RAMSTAGE |
| 39 | select SOC_INTEL_COMMON |
Duncan Laurie | a1c8b34d | 2015-09-08 16:12:44 -0700 | [diff] [blame] | 40 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Duncan Laurie | 4001f24 | 2016-06-07 16:40:19 -0700 | [diff] [blame] | 41 | select SOC_INTEL_COMMON_LPSS_I2C |
Aaron Durbin | c14a1a9 | 2016-06-28 15:41:07 -0500 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_NHLT |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 44 | select SMM_TSEG |
| 45 | select SMP |
| 46 | select SPI_FLASH |
| 47 | select SSE2 |
| 48 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 49 | select TSC_CONSTANT_RATE |
| 50 | select TSC_SYNC_MFENCE |
| 51 | select UDELAY_TSC |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 52 | select USE_GENERIC_FSP_CAR_INC |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 53 | |
| 54 | config BOOTBLOCK_CPU_INIT |
| 55 | string |
| 56 | default "soc/intel/skylake/bootblock/cpu.c" |
| 57 | |
| 58 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 59 | string |
| 60 | default "soc/intel/skylake/bootblock/systemagent.c" |
| 61 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 62 | config BOOTBLOCK_RESETS |
| 63 | string |
| 64 | default "soc/intel/common/reset.c" |
| 65 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 66 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 67 | string |
| 68 | default "soc/intel/skylake/bootblock/pch.c" |
| 69 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 70 | config CBFS_SIZE |
| 71 | hex |
| 72 | default 0x200000 |
| 73 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 74 | config CPU_ADDR_BITS |
| 75 | int |
| 76 | default 36 |
| 77 | |
Duncan Laurie | 4001f24 | 2016-06-07 16:40:19 -0700 | [diff] [blame] | 78 | config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ |
| 79 | int |
| 80 | default 120 |
| 81 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 82 | config DCACHE_RAM_BASE |
| 83 | hex "Base address of cache-as-RAM" |
| 84 | default 0xfef00000 |
| 85 | |
| 86 | config DCACHE_RAM_SIZE |
| 87 | hex "Length in bytes of cache-as-RAM" |
Aaron Durbin | ba69c77 | 2015-09-16 14:27:26 -0500 | [diff] [blame] | 88 | default 0x10000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 89 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 90 | The size of the cache-as-ram region required during bootblock |
| 91 | and/or romstage. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 92 | |
Subrata Banik | 086730b | 2015-12-02 11:42:04 +0530 | [diff] [blame] | 93 | config EXCLUDE_NATIVE_SD_INTERFACE |
| 94 | bool |
| 95 | default n |
| 96 | help |
| 97 | If you set this option to n, will not use native SD controller. |
| 98 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 99 | config HEAP_SIZE |
| 100 | hex |
| 101 | default 0x80000 |
| 102 | |
| 103 | config IED_REGION_SIZE |
| 104 | hex |
| 105 | default 0x400000 |
| 106 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 107 | config MMCONF_BASE_ADDRESS |
| 108 | hex "MMIO Base Address" |
| 109 | default 0xe0000000 |
| 110 | |
| 111 | config MONOTONIC_TIMER_MSR |
| 112 | def_bool y |
| 113 | select HAVE_MONOTONIC_TIMER |
| 114 | help |
| 115 | Provide a monotonic timer using the 24MHz MSR counter. |
| 116 | |
| 117 | config PRE_GRAPHICS_DELAY |
| 118 | int "Graphics initialization delay in ms" |
| 119 | default 0 |
| 120 | help |
| 121 | On some systems, coreboot boots so fast that connected monitors |
| 122 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 123 | VBIOS. On those systems we need to wait for a bit before executing |
| 124 | the VBIOS. |
| 125 | |
| 126 | config SERIAL_CPU_INIT |
| 127 | bool |
| 128 | default n |
| 129 | |
| 130 | config SERIRQ_CONTINUOUS_MODE |
| 131 | bool |
pchandri | 1d77c72 | 2015-09-09 17:22:09 -0700 | [diff] [blame] | 132 | default n |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 133 | help |
| 134 | If you set this option to y, the serial IRQ machine will be |
| 135 | operated in continuous mode. |
| 136 | |
| 137 | config SMM_RESERVED_SIZE |
| 138 | hex |
| 139 | default 0x200000 |
| 140 | |
| 141 | config SMM_TSEG_SIZE |
| 142 | hex |
| 143 | default 0x800000 |
| 144 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 145 | config VGA_BIOS_ID |
| 146 | string |
| 147 | default "8086,0406" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 148 | |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 149 | config UART_DEBUG |
| 150 | bool "Enable UART debug port." |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 151 | default n |
Martin Roth | 1afcb23 | 2015-08-15 17:36:15 -0600 | [diff] [blame] | 152 | select CONSOLE_SERIAL |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 153 | select DRIVERS_UART |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 154 | select DRIVERS_UART_8250MEM_32 |
| 155 | |
Aaron Durbin | 3953e39 | 2015-09-03 00:41:29 -0500 | [diff] [blame] | 156 | config CHIPSET_BOOTBLOCK_INCLUDE |
| 157 | string |
| 158 | default "soc/intel/skylake/bootblock/timestamp.inc" |
| 159 | |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 160 | config NHLT_DMIC_2CH |
| 161 | bool |
| 162 | default n |
| 163 | help |
| 164 | Include DSP firmware settings for 2 channel DMIC array. |
| 165 | |
| 166 | config NHLT_DMIC_4CH |
| 167 | bool |
| 168 | default n |
| 169 | help |
| 170 | Include DSP firmware settings for 4 channel DMIC array. |
| 171 | |
| 172 | config NHLT_NAU88L25 |
| 173 | bool |
| 174 | default n |
| 175 | help |
| 176 | Include DSP firmware settings for nau88l25 headset codec. |
| 177 | |
| 178 | config NHLT_MAX98357 |
| 179 | bool |
| 180 | default n |
| 181 | help |
| 182 | Include DSP firmware settings for max98357 amplifier. |
| 183 | |
| 184 | config NHLT_SSM4567 |
| 185 | bool |
| 186 | default n |
| 187 | help |
| 188 | Include DSP firmware settings for ssm4567 smart amplifier. |
| 189 | |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 190 | config DCACHE_RAM_SIZE_TOTAL |
| 191 | hex |
| 192 | default 0x40000 |
| 193 | |
| 194 | config SKIP_FSP_CAR |
Martin Roth | b00ddec | 2016-01-31 10:39:47 -0700 | [diff] [blame] | 195 | bool "Skip cache as RAM setup in FSP" |
| 196 | default y |
| 197 | help |
| 198 | Skip Cache as RAM setup in FSP. |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 199 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 200 | endif |