Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Ritul Guru | d3dae3d | 2022-04-04 13:33:01 +0530 | [diff] [blame] | 3 | config SOC_AMD_REMBRANDT_BASE |
| 4 | bool |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 5 | select ACPI_SOC_NVS |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 6 | select ARCH_X86 |
| 7 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Karthikeyan Ramasubramanian | b9a6223 | 2023-02-23 15:53:59 -0700 | [diff] [blame] | 8 | select CACHE_MRC_SETTINGS |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 9 | select DRIVERS_USB_ACPI |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 10 | select DRIVERS_USB_PCI_XHCI |
| 11 | select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING |
| 12 | select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING |
| 13 | select FSP_COMPRESS_FSP_S_LZ4 |
| 14 | select GENERIC_GPIO_LIB |
| 15 | select HAVE_ACPI_TABLES |
| 16 | select HAVE_CF9_RESET |
| 17 | select HAVE_EM100_SUPPORT |
| 18 | select HAVE_FSP_GOP |
| 19 | select HAVE_SMI_HANDLER |
| 20 | select IDT_IN_EVERY_STAGE |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 21 | select NO_DDR4 |
| 22 | select NO_DDR3 |
| 23 | select NO_DDR2 |
| 24 | select NO_LPDDR4 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 25 | select PARALLEL_MP_AP_WORK |
| 26 | select PLATFORM_USES_FSP2_0 |
| 27 | select PROVIDES_ROM_SHARING |
Karthikeyan Ramasubramanian | ef12976 | 2022-12-22 13:07:28 -0700 | [diff] [blame] | 28 | select PSP_INCLUDES_HSP |
Karthikeyan Ramasubramanian | 8ebb04c | 2022-07-14 17:29:06 -0600 | [diff] [blame] | 29 | select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Karthikeyan Ramasubramanian | b2af2e3 | 2022-08-04 14:16:38 -0600 | [diff] [blame] | 30 | select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 31 | select RESET_VECTOR_IN_RAM |
| 32 | select RTC |
| 33 | select SOC_AMD_COMMON |
Fred Reitberger | 81d3cde | 2022-02-10 09:31:26 -0500 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_ACP_GEN2 |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_ACPI |
Felix Held | 70f32bb | 2022-02-04 16:23:47 +0100 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_ACPI_ALIB |
Felix Held | 665476d | 2022-08-03 22:18:18 +0200 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_ACPI_CPPC |
Felix Held | e23c425 | 2023-03-07 00:03:46 +0100 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE |
Felix Held | af803a6 | 2022-06-22 18:22:16 +0200 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_ACPI_IVRS |
Felix Held | 716ccb7 | 2022-02-03 18:27:29 +0100 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_AOAC |
Fred Reitberger | 8b570bd | 2022-09-06 12:19:38 -0400 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_APOB |
| 44 | select SOC_AMD_COMMON_BLOCK_APOB_HASH |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | a63f859 | 2023-03-24 16:30:55 +0100 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H |
Felix Held | 75739d3 | 2022-02-03 18:44:27 +0100 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Felix Held | 65d73cc | 2022-10-13 20:58:47 +0200 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_EMMC |
Felix Held | c64f37d | 2022-02-12 17:30:59 +0100 | [diff] [blame] | 49 | select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Felix Held | c64f37d | 2022-02-12 17:30:59 +0100 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
Raul E Rangel | 5a5de33 | 2022-04-25 13:33:50 -0600 | [diff] [blame] | 52 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE |
Felix Held | 8e4742d | 2022-02-03 15:15:37 +0100 | [diff] [blame] | 53 | select SOC_AMD_COMMON_BLOCK_I2C |
Felix Held | 3bdbdb7 | 2022-02-02 22:55:34 +0100 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL |
Felix Held | 0eef54b | 2022-02-04 19:28:51 +0100 | [diff] [blame] | 55 | select SOC_AMD_COMMON_BLOCK_IOMMU |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 56 | select SOC_AMD_COMMON_BLOCK_LPC |
Karthikeyan Ramasubramanian | 5d5f682 | 2022-12-05 17:08:08 -0700 | [diff] [blame] | 57 | select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
Felix Held | 901481f | 2022-06-22 15:38:44 +0200 | [diff] [blame] | 58 | select SOC_AMD_COMMON_BLOCK_MCAX |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 59 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 60 | select SOC_AMD_COMMON_BLOCK_PCI |
Felix Held | ceefc74 | 2022-02-07 15:27:27 +0100 | [diff] [blame] | 61 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 62 | select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
Robert Zieba | b3b27f7 | 2022-10-03 14:50:55 -0600 | [diff] [blame] | 63 | select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 64 | select SOC_AMD_COMMON_BLOCK_PM |
| 65 | select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
| 66 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Martin Roth | 440c823 | 2023-02-01 14:27:18 -0700 | [diff] [blame] | 67 | select SOC_AMD_COMMON_BLOCK_RESET |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 68 | select SOC_AMD_COMMON_BLOCK_SMBUS |
| 69 | select SOC_AMD_COMMON_BLOCK_SMI |
| 70 | select SOC_AMD_COMMON_BLOCK_SMM |
Felix Held | 6f9e4ab | 2022-02-03 18:34:23 +0100 | [diff] [blame] | 71 | select SOC_AMD_COMMON_BLOCK_SMU |
Felix Held | 7a2c1c7 | 2023-01-12 23:11:22 +0100 | [diff] [blame] | 72 | select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 73 | select SOC_AMD_COMMON_BLOCK_SPI |
Martin Roth | 300338f | 2022-10-14 14:55:25 -0600 | [diff] [blame] | 74 | select SOC_AMD_COMMON_BLOCK_STB |
Felix Held | 23a398e | 2023-03-23 23:44:03 +0100 | [diff] [blame] | 75 | select SOC_AMD_COMMON_BLOCK_SVI3 |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 76 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | b0789ed | 2022-02-04 22:36:32 +0100 | [diff] [blame] | 77 | select SOC_AMD_COMMON_BLOCK_UART |
Felix Held | d9bb9fc | 2022-06-22 15:35:35 +0200 | [diff] [blame] | 78 | select SOC_AMD_COMMON_BLOCK_UCODE |
Robert Zieba | 3b28aef | 2022-09-15 15:25:55 -0600 | [diff] [blame] | 79 | select SOC_AMD_COMMON_BLOCK_XHCI |
Felix Held | 665476d | 2022-08-03 22:18:18 +0200 | [diff] [blame] | 80 | select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB |
Fred Reitberger | b77f9a3 | 2023-01-06 10:46:23 -0500 | [diff] [blame] | 81 | select SOC_AMD_COMMON_FSP_DMI_TABLES |
| 82 | select SOC_AMD_COMMON_FSP_PCI |
Fred Reitberger | 41c7e31 | 2023-01-11 15:11:08 -0500 | [diff] [blame] | 83 | select SOC_AMD_COMMON_FSP_PRELOAD_FSPS |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 84 | select SSE2 |
| 85 | select UDK_2017_BINDING |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 86 | select USE_DDR5 |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 87 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 88 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 89 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 90 | select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Matt DeVillier | 65a4445 | 2023-02-16 09:57:40 -0600 | [diff] [blame] | 91 | select VBOOT_MUST_REQUEST_DISPLAY if VBOOT |
Karthikeyan Ramasubramanian | 06d5b8b | 2022-10-27 22:50:07 -0600 | [diff] [blame] | 92 | select VBOOT_X86_SHA256_ACCELERATION if VBOOT |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 93 | select X86_AMD_FIXED_MTRRS |
| 94 | select X86_INIT_NEED_1_SIPI |
| 95 | |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 96 | config SOC_AMD_MENDOCINO |
| 97 | bool |
| 98 | select SOC_AMD_REMBRANDT_BASE |
| 99 | help |
| 100 | AMD Mendocino support |
| 101 | |
| 102 | config SOC_AMD_REMBRANDT |
| 103 | bool |
| 104 | select SOC_AMD_REMBRANDT_BASE |
| 105 | help |
| 106 | AMD Rembrandt support |
| 107 | |
| 108 | |
| 109 | if SOC_AMD_REMBRANDT_BASE |
| 110 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 111 | config CHIPSET_DEVICETREE |
| 112 | string |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame] | 113 | default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO |
| 114 | default "soc/amd/mendocino/chipset_rembrandt.cb" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 115 | |
| 116 | config EARLY_RESERVED_DRAM_BASE |
| 117 | hex |
| 118 | default 0x2000000 |
| 119 | help |
| 120 | This variable defines the base address of the DRAM which is reserved |
| 121 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 122 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 123 | not use it, thus preventing corruption of OS memory in case of S3 |
| 124 | resume. |
| 125 | |
| 126 | config EARLYRAM_BSP_STACK_SIZE |
| 127 | hex |
| 128 | default 0x1000 |
| 129 | |
| 130 | config PSP_APOB_DRAM_ADDRESS |
| 131 | hex |
| 132 | default 0x2001000 |
| 133 | help |
| 134 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 135 | Block. |
| 136 | |
Fred Reitberger | 475e282 | 2022-07-14 11:06:30 -0400 | [diff] [blame] | 137 | config PSP_APOB_DRAM_SIZE |
| 138 | hex |
Fred Reitberger | fdb0758 | 2022-07-15 08:05:56 -0400 | [diff] [blame] | 139 | default 0x1E000 |
Fred Reitberger | 475e282 | 2022-07-14 11:06:30 -0400 | [diff] [blame] | 140 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 141 | config PSP_SHAREDMEM_BASE |
| 142 | hex |
Fred Reitberger | fdb0758 | 2022-07-15 08:05:56 -0400 | [diff] [blame] | 143 | default 0x201F000 if VBOOT |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 144 | default 0x0 |
| 145 | help |
| 146 | This variable defines the base address in DRAM memory where PSP copies |
| 147 | the vboot workbuf. This is used in the linker script to have a static |
| 148 | allocation for the buffer as well as for adding relevant entries in |
| 149 | the BIOS directory table for the PSP. |
| 150 | |
| 151 | config PSP_SHAREDMEM_SIZE |
| 152 | hex |
| 153 | default 0x8000 if VBOOT |
| 154 | default 0x0 |
| 155 | help |
| 156 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 157 | any logs or timestamps back to coreboot. This will be copied |
| 158 | into main memory by the PSP and will be available when the x86 is |
| 159 | started. The workbuf's base depends on the address of the reset |
| 160 | vector. |
| 161 | |
Felix Held | 5561468 | 2022-01-25 04:31:15 +0100 | [diff] [blame] | 162 | config PRE_X86_CBMEM_CONSOLE_SIZE |
| 163 | hex |
Karthikeyan Ramasubramanian | 4763a5a4 | 2022-11-17 23:07:28 -0700 | [diff] [blame] | 164 | default 0x1000 |
Felix Held | 5561468 | 2022-01-25 04:31:15 +0100 | [diff] [blame] | 165 | help |
| 166 | Size of the CBMEM console used in PSP verstage. |
| 167 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 168 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 169 | hex |
| 170 | default 0x1600 |
| 171 | help |
| 172 | Increase this value if preram cbmem console is getting truncated |
| 173 | |
| 174 | config CBFS_MCACHE_SIZE |
| 175 | hex |
Karthikeyan Ramasubramanian | 4763a5a4 | 2022-11-17 23:07:28 -0700 | [diff] [blame] | 176 | default 0x3800 if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 177 | |
| 178 | config C_ENV_BOOTBLOCK_SIZE |
| 179 | hex |
| 180 | default 0x10000 |
| 181 | help |
| 182 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 183 | This variable controls the DRAM allocation size in linker script |
| 184 | for bootblock stage. |
| 185 | |
| 186 | config ROMSTAGE_ADDR |
| 187 | hex |
| 188 | default 0x2040000 |
| 189 | help |
| 190 | Sets the address in DRAM where romstage should be loaded. |
| 191 | |
| 192 | config ROMSTAGE_SIZE |
| 193 | hex |
| 194 | default 0x80000 |
| 195 | help |
| 196 | Sets the size of DRAM allocation for romstage in linker script. |
| 197 | |
| 198 | config FSP_M_ADDR |
| 199 | hex |
| 200 | default 0x20C0000 |
| 201 | help |
| 202 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 203 | performs relocation of FSP-M to this address. |
| 204 | |
| 205 | config FSP_M_SIZE |
| 206 | hex |
| 207 | default 0xC0000 |
| 208 | help |
| 209 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 210 | |
| 211 | config FSP_TEMP_RAM_SIZE |
| 212 | hex |
| 213 | default 0x40000 |
| 214 | help |
| 215 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 216 | |
| 217 | config VERSTAGE_ADDR |
| 218 | hex |
| 219 | depends on VBOOT_SEPARATE_VERSTAGE |
| 220 | default 0x2180000 |
| 221 | help |
| 222 | Sets the address in DRAM where verstage should be loaded if running |
| 223 | as a separate stage on x86. |
| 224 | |
| 225 | config VERSTAGE_SIZE |
| 226 | hex |
| 227 | depends on VBOOT_SEPARATE_VERSTAGE |
| 228 | default 0x80000 |
| 229 | help |
| 230 | Sets the size of DRAM allocation for verstage in linker script if |
| 231 | running as a separate stage on x86. |
| 232 | |
| 233 | config ASYNC_FILE_LOADING |
| 234 | bool "Loads files from SPI asynchronously" |
| 235 | select COOP_MULTITASKING |
| 236 | select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 237 | select CBFS_PRELOAD |
| 238 | help |
| 239 | When enabled, the platform will use the LPC SPI DMA controller to |
| 240 | asynchronously load contents from the SPI ROM. This will improve |
| 241 | boot time because the CPUs can be performing useful work while the |
| 242 | SPI contents are being preloaded. |
| 243 | |
| 244 | config CBFS_CACHE_SIZE |
| 245 | hex |
| 246 | default 0x40000 if CBFS_PRELOAD |
| 247 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 248 | config RO_REGION_ONLY |
| 249 | string |
| 250 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 251 | default "apu/amdfw" |
| 252 | |
| 253 | config ECAM_MMCONF_BASE_ADDRESS |
| 254 | default 0xF8000000 |
| 255 | |
| 256 | config ECAM_MMCONF_BUS_NUMBER |
| 257 | default 64 |
| 258 | |
| 259 | config MAX_CPUS |
| 260 | int |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame] | 261 | default 8 if SOC_AMD_MENDOCINO |
Ritul Guru | d3dae3d | 2022-04-04 13:33:01 +0530 | [diff] [blame] | 262 | default 16 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 263 | help |
| 264 | Maximum number of threads the platform can have. |
| 265 | |
Felix Held | e68ddc7 | 2023-02-14 23:02:09 +0100 | [diff] [blame] | 266 | config VGA_BIOS_ID |
| 267 | string |
| 268 | default "1002,1506" if SOC_AMD_MENDOCINO |
| 269 | help |
| 270 | The default VGA BIOS PCI vendor/device ID of the GPU and VBIOS. |
| 271 | |
| 272 | config VGA_BIOS_FILE |
| 273 | string |
| 274 | default "3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin" if SOC_AMD_MENDOCINO |
| 275 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 276 | config CONSOLE_UART_BASE_ADDRESS |
| 277 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 278 | hex |
| 279 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 280 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
Felix Held | b1fe9de | 2022-01-12 23:18:54 +0100 | [diff] [blame] | 281 | default 0xfedce000 if UART_FOR_CONSOLE = 2 |
| 282 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
| 283 | default 0xfedd1000 if UART_FOR_CONSOLE = 4 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 284 | |
| 285 | config SMM_TSEG_SIZE |
| 286 | hex |
| 287 | default 0x800000 if HAVE_SMI_HANDLER |
| 288 | default 0x0 |
| 289 | |
| 290 | config SMM_RESERVED_SIZE |
| 291 | hex |
| 292 | default 0x180000 |
| 293 | |
| 294 | config SMM_MODULE_STACK_SIZE |
| 295 | hex |
| 296 | default 0x800 |
| 297 | |
| 298 | config ACPI_BERT |
| 299 | bool "Build ACPI BERT Table" |
| 300 | default y |
| 301 | depends on HAVE_ACPI_TABLES |
| 302 | help |
| 303 | Report Machine Check errors identified in POST to the OS in an |
| 304 | ACPI Boot Error Record Table. |
| 305 | |
| 306 | config ACPI_BERT_SIZE |
| 307 | hex |
| 308 | default 0x4000 if ACPI_BERT |
| 309 | default 0x0 |
| 310 | help |
| 311 | Specify the amount of DRAM reserved for gathering the data used to |
| 312 | generate the ACPI table. |
| 313 | |
| 314 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 315 | int |
| 316 | default 150 |
| 317 | |
| 318 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 319 | def_bool n |
| 320 | help |
| 321 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 322 | which indicates a board level ROM transaction request. This |
| 323 | removes arbitration with board and assumes the chipset controls |
| 324 | the SPI flash bus entirely. |
| 325 | |
| 326 | config DISABLE_KEYBOARD_RESET_PIN |
| 327 | bool |
| 328 | help |
Martin Roth | 9ceac74 | 2023-02-08 14:26:02 -0700 | [diff] [blame] | 329 | Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L. |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 330 | |
Chris.Wang | 9ac0984 | 2022-12-13 14:31:38 +0800 | [diff] [blame] | 331 | config FEATURE_DYNAMIC_DPTC |
| 332 | bool |
| 333 | depends on SOC_AMD_COMMON_BLOCK_ACPI_DPTC |
| 334 | help |
| 335 | Selected by mainboards that implement support for ALIB |
| 336 | to enable dynamic DPTC. |
| 337 | |
| 338 | config FEATURE_TABLET_MODE_DPTC |
| 339 | bool |
| 340 | depends on SOC_AMD_COMMON_BLOCK_ACPI_DPTC |
| 341 | help |
| 342 | Selected by mainboards that implement support for ALIB to |
| 343 | switch default and tablet mode. |
| 344 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 345 | menu "PSP Configuration Options" |
| 346 | |
| 347 | config AMD_FWM_POSITION_INDEX |
| 348 | int "Firmware Directory Table location (0 to 5)" |
| 349 | range 0 5 |
| 350 | default 0 if BOARD_ROMSIZE_KB_512 |
| 351 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 352 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 353 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 354 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 355 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 356 | help |
| 357 | Typically this is calculated by the ROM size, but there may |
| 358 | be situations where you want to put the firmware directory |
| 359 | table in a different location. |
| 360 | 0: 512 KB - 0xFFFA0000 |
| 361 | 1: 1 MB - 0xFFF20000 |
| 362 | 2: 2 MB - 0xFFE20000 |
| 363 | 3: 4 MB - 0xFFC20000 |
| 364 | 4: 8 MB - 0xFF820000 |
| 365 | 5: 16 MB - 0xFF020000 |
| 366 | |
| 367 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 368 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 369 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 370 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 371 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 372 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 373 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 374 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 375 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 376 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 377 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 378 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 379 | |
| 380 | config AMDFW_CONFIG_FILE |
Karthikeyan Ramasubramanian | 9cb0a05 | 2022-03-21 17:49:11 -0600 | [diff] [blame] | 381 | string "AMD PSP Firmware config file" |
Jon Murphy | 4f73242 | 2022-08-05 15:43:44 -0600 | [diff] [blame] | 382 | default "src/soc/amd/mendocino/fw.cfg" |
Karthikeyan Ramasubramanian | 9cb0a05 | 2022-03-21 17:49:11 -0600 | [diff] [blame] | 383 | help |
| 384 | Specify the path/location of AMD PSP Firmware config file. |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 385 | |
| 386 | config PSP_DISABLE_POSTCODES |
| 387 | bool "Disable PSP post codes" |
| 388 | help |
| 389 | Disables the output of port80 post codes from PSP. |
| 390 | |
| 391 | config PSP_POSTCODES_ON_ESPI |
| 392 | bool "Use eSPI bus for PSP post codes" |
| 393 | default y |
| 394 | depends on !PSP_DISABLE_POSTCODES |
| 395 | help |
| 396 | Select to send PSP port80 post codes on eSPI bus. |
| 397 | If not selected, PSP port80 codes will be sent on LPC bus. |
| 398 | |
| 399 | config PSP_LOAD_MP2_FW |
| 400 | bool |
| 401 | default n |
| 402 | help |
| 403 | Include the MP2 firmwares and configuration into the PSP build. |
| 404 | |
| 405 | If unsure, answer 'n' |
| 406 | |
| 407 | config PSP_UNLOCK_SECURE_DEBUG |
| 408 | bool "Unlock secure debug" |
| 409 | default y |
| 410 | help |
| 411 | Select this item to enable secure debug options in PSP. |
| 412 | |
| 413 | config HAVE_PSP_WHITELIST_FILE |
| 414 | bool "Include a debug whitelist file in PSP build" |
| 415 | default n |
| 416 | help |
| 417 | Support secured unlock prior to reset using a whitelisted |
| 418 | serial number. This feature requires a signed whitelist image |
| 419 | and bootloader from AMD. |
| 420 | |
| 421 | If unsure, answer 'n' |
| 422 | |
| 423 | config PSP_WHITELIST_FILE |
| 424 | string "Debug whitelist file path" |
| 425 | depends on HAVE_PSP_WHITELIST_FILE |
Marshall Dawson | 84fef89 | 2022-08-05 12:13:49 -0600 | [diff] [blame] | 426 | default "site-local/3rdparty/amd_blobs/mendocino/PSP/wtl-mdn.sbin" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 427 | |
Karthikeyan Ramasubramanian | 8ee9429 | 2022-04-01 17:21:14 -0600 | [diff] [blame] | 428 | config HAVE_SPL_FILE |
| 429 | bool "Have a mainboard specific SPL table file" |
| 430 | default n |
| 431 | help |
| 432 | Have a mainboard specific Security Patch Level (SPL) table file. SPL file |
| 433 | is required to support PSP FW anti-rollback and needs to be created by AMD. |
| 434 | The default SPL file applies to all boards that use the concerned SoC and |
| 435 | is dropped under 3rdparty/blobs. The mainboard specific SPL file override |
| 436 | can be applied through SPL_TABLE_FILE config. |
| 437 | |
| 438 | If unsure, answer 'n' |
| 439 | |
| 440 | config SPL_TABLE_FILE |
| 441 | string "SPL table file" |
| 442 | depends on HAVE_SPL_FILE |
Marshall Dawson | 26d7d73 | 2022-08-05 12:44:03 -0600 | [diff] [blame] | 443 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" |
Karthikeyan Ramasubramanian | 8ee9429 | 2022-04-01 17:21:14 -0600 | [diff] [blame] | 444 | |
Felix Held | 40a38cc | 2022-09-12 16:18:45 +0200 | [diff] [blame] | 445 | config HAVE_SPL_RW_AB_FILE |
| 446 | bool "Have a separate mainboard-specific SPL file in RW A/B partitions" |
| 447 | default n |
| 448 | depends on HAVE_SPL_FILE |
| 449 | depends on VBOOT_SLOTS_RW_AB |
| 450 | help |
| 451 | Have separate mainboard-specific Security Patch Level (SPL) table |
| 452 | file for the RW A/B FMAP partitions. See the help text of |
| 453 | HAVE_SPL_FILE for a more detailed description. |
| 454 | |
| 455 | config SPL_RW_AB_TABLE_FILE |
| 456 | string "Separate SPL table file for RW A/B partitions" |
| 457 | depends on HAVE_SPL_RW_AB_FILE |
| 458 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_MDN.sbin" |
| 459 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 460 | config PSP_SOFTFUSE_BITS |
| 461 | string "PSP Soft Fuse bits to enable" |
Felix Held | ed69450 | 2022-06-22 15:09:23 +0200 | [diff] [blame] | 462 | default "34 28 6" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 463 | help |
| 464 | Space separated list of Soft Fuse bits to enable. |
| 465 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 466 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 467 | (Set by PSP_DISABLE_PORT80) |
Felix Held | c357900 | 2022-03-23 22:15:56 +0100 | [diff] [blame] | 468 | Bit 15: PSP debug output destination: |
| 469 | 0=SoC MMIO UART, 1=IO port 0x3F8 |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 470 | Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| 471 | |
| 472 | See #55758 (NDA) for additional bit definitions. |
| 473 | |
| 474 | config PSP_VERSTAGE_FILE |
| 475 | string "Specify the PSP_verstage file path" |
| 476 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 477 | default "\$(obj)/psp_verstage.bin" |
| 478 | help |
| 479 | Add psp_verstage file to the build & PSP Directory Table |
| 480 | |
| 481 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 482 | string "Specify the PSP_verstage Signature Token file path" |
| 483 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 484 | default "" |
| 485 | help |
| 486 | Add psp_verstage signature token to the build & PSP Directory Table |
| 487 | |
| 488 | endmenu |
| 489 | |
| 490 | config VBOOT |
| 491 | select VBOOT_VBNV_CMOS |
| 492 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 493 | |
| 494 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 495 | def_bool n |
| 496 | depends on VBOOT |
| 497 | select ARCH_VERSTAGE_ARMV7 |
| 498 | help |
| 499 | Runs verstage on the PSP. Only available on |
Jon Murphy | c4e9045 | 2022-06-28 10:36:23 -0600 | [diff] [blame] | 500 | certain ChromeOS branded parts from AMD. |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 501 | |
| 502 | config VBOOT_HASH_BLOCK_SIZE |
| 503 | hex |
| 504 | default 0x9000 |
| 505 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 506 | help |
| 507 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 508 | spent in the overhead of doing svc calls, increasing the hash block |
| 509 | size significantly cuts the verstage hashing time as seen below. |
| 510 | |
| 511 | 4k takes 180ms |
| 512 | 16k takes 44ms |
| 513 | 32k takes 33.7ms |
| 514 | 36k takes 32.5ms |
| 515 | There's actually still room for an even bigger stack, but we've |
| 516 | reached a point of diminishing returns. |
| 517 | |
| 518 | config CMOS_RECOVERY_BYTE |
| 519 | hex |
| 520 | default 0x51 |
| 521 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 522 | help |
| 523 | If the workbuf is not passed from the PSP to coreboot, set the |
| 524 | recovery flag and reboot. The PSP will read this byte, mark the |
| 525 | recovery request in VBNV, and reset the system into recovery mode. |
| 526 | |
| 527 | This is the byte before the default first byte used by VBNV |
| 528 | (0x26 + 0x0E - 1) |
| 529 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 530 | if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 531 | |
| 532 | config RWA_REGION_ONLY |
| 533 | string |
Karthikeyan Ramasubramanian | 716c8f0 | 2022-12-15 14:57:05 -0700 | [diff] [blame] | 534 | default "apu/amdfw_a apu/amdfw_a_body" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 535 | help |
| 536 | Add a space-delimited list of filenames that should only be in the |
| 537 | RW-A section. |
| 538 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 539 | endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 540 | |
| 541 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 542 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 543 | config RWB_REGION_ONLY |
| 544 | string |
Karthikeyan Ramasubramanian | 716c8f0 | 2022-12-15 14:57:05 -0700 | [diff] [blame] | 545 | default "apu/amdfw_b apu/amdfw_b_body" |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 546 | help |
| 547 | Add a space-delimited list of filenames that should only be in the |
| 548 | RW-B section. |
| 549 | |
| 550 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 551 | |
Ritul Guru | d3dae3d | 2022-04-04 13:33:01 +0530 | [diff] [blame] | 552 | endif # SOC_AMD_REMBRANDT_BASE |