blob: 84c2b6f5347aa94bf645731c973069328f2ff78c [file] [log] [blame]
Lee Leahyc4210412015-06-29 11:37:56 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
6 * Copyright (C) 2015 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Lee Leahyc4210412015-06-29 11:37:56 -070016 */
17
Lee Leahyc4210412015-06-29 11:37:56 -070018#include <string.h>
pchandrie57e7262015-09-14 14:11:38 -070019#include <gpio.h>
Lee Leahyc4210412015-06-29 11:37:56 -070020#include <soc/pei_data.h>
21#include <soc/pei_wrapper.h>
Lee Leahyc4210412015-06-29 11:37:56 -070022#include <soc/romstage.h>
Wenkai Du1105fad2015-08-21 13:11:00 -070023#include "gpio.h"
Lee Leahyc4210412015-06-29 11:37:56 -070024#include "spd/spd.h"
25
26void mainboard_romstage_entry(struct romstage_params *params)
27{
pchandrie57e7262015-09-14 14:11:38 -070028 /* PCH_MEM_CFG[3:0] */
29 gpio_t spd_gpios[] = {
30 GPIO_MEM_CONFIG_0,
31 GPIO_MEM_CONFIG_1,
32 GPIO_MEM_CONFIG_2,
33 GPIO_MEM_CONFIG_3,
34 };
35
pchandrie57e7262015-09-14 14:11:38 -070036 params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
37 ARRAY_SIZE(spd_gpios));
Lee Leahyc4210412015-06-29 11:37:56 -070038 /* Fill out PEI DATA */
39 mainboard_fill_pei_data(params->pei_data);
40 mainboard_fill_spd_data(params->pei_data);
41 /* Initliaze memory */
42 romstage_common(params);
43}
44
Duncan Laurie74b964e2015-09-04 10:41:02 -070045void mainboard_memory_init_params(struct romstage_params *params,
46 MEMORY_INIT_UPD *memory_params)
Lee Leahyc4210412015-06-29 11:37:56 -070047{
48 if (params->pei_data->spd_data[0][0][0] != 0) {
49 memory_params->MemorySpdPtr00 =
50 (UINT32)(params->pei_data->spd_data[0][0]);
51 memory_params->MemorySpdPtr10 =
52 (UINT32)(params->pei_data->spd_data[1][0]);
Lee Leahyc4210412015-06-29 11:37:56 -070053 }
54 memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
55 sizeof(params->pei_data->dq_map[0]));
56 memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
57 sizeof(params->pei_data->dq_map[1]));
58 memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
59 sizeof(params->pei_data->dqs_map[0]));
60 memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
61 sizeof(params->pei_data->dqs_map[1]));
62 memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
63 sizeof(params->pei_data->RcompResistor));
64 memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
65 sizeof(params->pei_data->RcompTarget));
66 memory_params->MemorySpdDataLen = SPD_LEN;
67 memory_params->DqPinsInterleaved = FALSE;
68}