blob: 95561aa60207f7f28afafd359d6c762aed9e98c5 [file] [log] [blame]
Lee Leahyc4210412015-06-29 11:37:56 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2014 Google Inc.
6 * Copyright (C) 2015 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <cbfs.h>
23#include <console/console.h>
24#include <string.h>
25#include <ec/google/chromeec/ec.h>
26#include <soc/cpu.h>
27#include <soc/gpio.h>
28#include <soc/pei_data.h>
29#include <soc/pei_wrapper.h>
30#include <soc/pm.h>
31#include <soc/romstage.h>
32#include "spd/spd.h"
33
34void mainboard_romstage_entry(struct romstage_params *params)
35{
36 post_code(0x31);
37 /* Fill out PEI DATA */
38 mainboard_fill_pei_data(params->pei_data);
39 mainboard_fill_spd_data(params->pei_data);
40 /* Initliaze memory */
41 romstage_common(params);
42}
43
44void mainboard_memory_init_params(
45 struct romstage_params *params,
46 MEMORY_INIT_UPD *memory_params)
47{
48 if (params->pei_data->spd_data[0][0][0] != 0) {
49 memory_params->MemorySpdPtr00 =
50 (UINT32)(params->pei_data->spd_data[0][0]);
51 memory_params->MemorySpdPtr10 =
52 (UINT32)(params->pei_data->spd_data[1][0]);
53 printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
54 memory_params->MemorySpdPtr00);
55 printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n",
56 memory_params->MemorySpdPtr01);
57 printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
58 memory_params->MemorySpdPtr10);
59 printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n",
60 memory_params->MemorySpdPtr11);
61 }
62 memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
63 sizeof(params->pei_data->dq_map[0]));
64 memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
65 sizeof(params->pei_data->dq_map[1]));
66 memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
67 sizeof(params->pei_data->dqs_map[0]));
68 memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
69 sizeof(params->pei_data->dqs_map[1]));
70 memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
71 sizeof(params->pei_data->RcompResistor));
72 memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
73 sizeof(params->pei_data->RcompTarget));
74 memory_params->MemorySpdDataLen = SPD_LEN;
75 memory_params->DqPinsInterleaved = FALSE;
76}