commit 74b964ec4ace463d0b221a369a754bc86776e594
author Duncan Laurie <dlaurie@chromium.org> Fri Sep 04 10:41:02 2015 -0700
committer Patrick Georgi <pgeorgi@google.com> Thu Sep 10 09:52:06 2015 +0000
tree 3a5bc109379703d7282a3bb33f84eb7a0904f76f
parent 963bfa7a0f36d25b22ff221ddc3f1a537bb655a2

kunimitsu: Clean up mainboard code to match glados

Clean up the intel/kunimitsu mainboard code to match the code
and cleanups in glados.  Many of these are trivial changes that
do not impact things in a meaningful way but will make it easier
to diff the code and keep the mainboards in sync.

- use relative path for mainboard includes to make porting easier
- fix trivial style issues to match glados so diffs are clean
- pull GPIO configuration into gpio.h and use from there
- remove thermal.h as it is not used on this board
- make info message BIOS_INFO instead of BIOS_ERR
- add support for SPD manufacturer and part number in SMBIOS

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot

Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be
Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297752
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/intel/kunimitsu/romstage.c

diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c
index 269f297..af16dce 100644
--- a/src/mainboard/intel/kunimitsu/romstage.c
+++ b/src/mainboard/intel/kunimitsu/romstage.c
@@ -21,13 +21,12 @@
 
 #include <cbfs.h>
 #include <console/console.h>
+#include <memory_info.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/cpu.h>
 #include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
-#include <soc/pm.h>
 #include <soc/romstage.h>
 #include "gpio.h"
 #include "spd/spd.h"
@@ -45,7 +44,6 @@
 	/* Ensure the EC and PD are in the right mode for recovery */
 	google_chromeec_early_init();
 
-	post_code(0x31);
 	early_config_gpio();
 
 	/* Fill out PEI DATA */
@@ -55,23 +53,14 @@
 	romstage_common(params);
 }
 
-void mainboard_memory_init_params(
-	struct romstage_params *params,
-	MEMORY_INIT_UPD *memory_params)
+void mainboard_memory_init_params(struct romstage_params *params,
+				  MEMORY_INIT_UPD *memory_params)
 {
 	if (params->pei_data->spd_data[0][0][0] != 0) {
 		memory_params->MemorySpdPtr00 =
 				(UINT32)(params->pei_data->spd_data[0][0]);
 		memory_params->MemorySpdPtr10 =
 				(UINT32)(params->pei_data->spd_data[1][0]);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
-				memory_params->MemorySpdPtr00);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n",
-				memory_params->MemorySpdPtr01);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
-				memory_params->MemorySpdPtr10);
-		printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n",
-				memory_params->MemorySpdPtr11);
 	}
 	memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
 			sizeof(params->pei_data->dq_map[0]));
@@ -88,3 +77,18 @@
 	memory_params->MemorySpdDataLen = SPD_LEN;
 	memory_params->DqPinsInterleaved = FALSE;
 }
+
+void mainboard_add_dimm_info(struct romstage_params *params,
+			     struct memory_info *mem_info,
+			     int channel, int dimm, int index)
+{
+	/* Set the manufacturer */
+	memcpy(&mem_info->dimm[index].mod_id,
+	       &params->pei_data->spd_data[channel][dimm][SPD_MANU_OFF],
+	       sizeof(mem_info->dimm[index].mod_id));
+
+	/* Set the module part number */
+	memcpy(mem_info->dimm[index].module_part_number,
+	       &params->pei_data->spd_data[channel][dimm][SPD_PART_OFF],
+	       sizeof(mem_info->dimm[index].module_part_number));
+}