| Lee Leahy | 274d20a | 2016-05-15 13:52:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| Lee Leahy | 5ef051a | 2016-04-29 15:16:54 -0700 | [diff] [blame^] | 16 | /* PCIe reset pin */ |
| 17 | #define GEN2_PCI_RESET_RESUMEWELL_GPIO 0 |
| 18 | |
| Lee Leahy | 274d20a | 2016-05-15 13:52:36 -0700 | [diff] [blame] | 19 | static const struct reg_script gen2_gpio_init[] = { |
| 20 | /* Initialize the legacy GPIO controller */ |
| 21 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03), |
| 22 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x03), |
| 23 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00), |
| 24 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00), |
| 25 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00), |
| 26 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00), |
| 27 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00), |
| 28 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03), |
| 29 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00), |
| 30 | |
| 31 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f), |
| 32 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x1c), |
| 33 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x02), |
| 34 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00), |
| 35 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00), |
| 36 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00), |
| 37 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00), |
| 38 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f), |
| 39 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00), |
| 40 | |
| 41 | /* Initialize the GPIO controller */ |
| 42 | REG_GPIO_WRITE(GPIO_INTEN, 0), |
| 43 | REG_GPIO_WRITE(GPIO_INTSTATUS, 0), |
| 44 | REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5), |
| 45 | REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 5), |
| 46 | REG_GPIO_WRITE(GPIO_INTMASK, 0), |
| 47 | REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0), |
| 48 | REG_GPIO_WRITE(GPIO_INT_POLARITY, 0), |
| 49 | REG_GPIO_WRITE(GPIO_DEBOUNCE, 0), |
| 50 | REG_GPIO_WRITE(GPIO_LS_SYNC, 0), |
| 51 | |
| 52 | REG_SCRIPT_END |
| 53 | }; |
| Lee Leahy | 15843bd | 2016-05-15 15:05:56 -0700 | [diff] [blame] | 54 | |
| 55 | static const struct reg_script gen2_i2c_init[] = { |
| 56 | /* Route I2C to Arduino Shield connector: |
| 57 | * Set AMUX1_IN (EXP2.P1_4) low |
| 58 | * Configure AMUX1_IN (EXP2.P1_4) as an output |
| 59 | * |
| 60 | * I2C_SDA -> ANALOG_A4 |
| 61 | * I2C_SCL -> ANALOG_A5 |
| 62 | */ |
| 63 | REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_OUTPUT1, ~BIT4), |
| 64 | REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, ~BIT4), |
| 65 | |
| 66 | /* Set all GPIO expander pins connected to the Reset Button as inputs |
| 67 | * Configure Reset Button(EXP1.P1_7) as an input |
| 68 | * Disable pullup on Reset Button(EXP1.P1_7) |
| 69 | * Configure Reset Button(EXP2.P1_7) as an input |
| 70 | * Disable pullup on Reset Button(EXP2.P1_7) |
| 71 | */ |
| 72 | REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7), |
| 73 | REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7), |
| 74 | REG_I2C_OR(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, BIT7), |
| 75 | REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7), |
| 76 | |
| 77 | REG_SCRIPT_END |
| 78 | }; |