| Lee Leahy | 274d20a | 2016-05-15 13:52:36 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | static const struct reg_script gen2_gpio_init[] = { |
| 17 | /* Initialize the legacy GPIO controller */ |
| 18 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03), |
| 19 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x03), |
| 20 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00), |
| 21 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00), |
| 22 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00), |
| 23 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00), |
| 24 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00), |
| 25 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03), |
| 26 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00), |
| 27 | |
| 28 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f), |
| 29 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x1c), |
| 30 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x02), |
| 31 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00), |
| 32 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00), |
| 33 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00), |
| 34 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00), |
| 35 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f), |
| 36 | REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00), |
| 37 | |
| 38 | /* Initialize the GPIO controller */ |
| 39 | REG_GPIO_WRITE(GPIO_INTEN, 0), |
| 40 | REG_GPIO_WRITE(GPIO_INTSTATUS, 0), |
| 41 | REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5), |
| 42 | REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 5), |
| 43 | REG_GPIO_WRITE(GPIO_INTMASK, 0), |
| 44 | REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0), |
| 45 | REG_GPIO_WRITE(GPIO_INT_POLARITY, 0), |
| 46 | REG_GPIO_WRITE(GPIO_DEBOUNCE, 0), |
| 47 | REG_GPIO_WRITE(GPIO_LS_SYNC, 0), |
| 48 | |
| 49 | REG_SCRIPT_END |
| 50 | }; |