Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/acpi.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <delay.h> |
| 22 | #include <cpu/intel/model_206ax/model_206ax.h> |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 23 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_ids.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 27 | #include <stdlib.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 28 | #include <cpu/cpu.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 29 | #include "chip.h" |
| 30 | #include "sandybridge.h" |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 31 | #include <cpu/intel/smm/gen1/smi.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 32 | |
| 33 | static int bridge_revision_id = -1; |
| 34 | |
Kyösti Mälkki | f7bfc34 | 2013-10-18 11:02:46 +0300 | [diff] [blame] | 35 | /* IGD UMA memory */ |
| 36 | static uint64_t uma_memory_base = 0; |
| 37 | static uint64_t uma_memory_size = 0; |
| 38 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 39 | int bridge_silicon_revision(void) |
| 40 | { |
| 41 | if (bridge_revision_id < 0) { |
| 42 | uint8_t stepping = cpuid_eax(1) & 0xf; |
| 43 | uint8_t bridge_id = pci_read_config16( |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 44 | pcidev_on_root(0, 0), |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | PCI_DEVICE_ID) & 0xf0; |
| 46 | bridge_revision_id = bridge_id | stepping; |
| 47 | } |
| 48 | return bridge_revision_id; |
| 49 | } |
| 50 | |
| 51 | /* Reserve everything between A segment and 1MB: |
| 52 | * |
| 53 | * 0xa0000 - 0xbffff: legacy VGA |
| 54 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 55 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 56 | */ |
| 57 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 58 | static const int legacy_hole_size_k = 384; |
| 59 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 60 | static int get_pcie_bar(u32 *base) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 61 | { |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 62 | struct device *dev; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 63 | u32 pciexbar_reg; |
| 64 | |
| 65 | *base = 0; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 66 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 67 | dev = pcidev_on_root(0, 0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 68 | if (!dev) |
| 69 | return 0; |
| 70 | |
| 71 | pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
| 72 | |
| 73 | if (!(pciexbar_reg & (1 << 0))) |
| 74 | return 0; |
| 75 | |
| 76 | switch ((pciexbar_reg >> 1) & 3) { |
| 77 | case 0: // 256MB |
| 78 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 79 | return 256; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 80 | case 1: // 128M |
| 81 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 82 | return 128; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 83 | case 2: // 64M |
| 84 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 85 | return 64; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | return 0; |
| 89 | } |
| 90 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 91 | static void add_fixed_resources(struct device *dev, int index) |
| 92 | { |
Kyösti Mälkki | 7f189cc | 2012-07-27 13:12:03 +0300 | [diff] [blame] | 93 | mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 94 | |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 95 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 96 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 97 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 98 | (0x100000 - 0xc0000) >> 10); |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 99 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 100 | #if CONFIG(CHROMEOS_RAMOOPS) |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 101 | reserved_ram_resource(dev, index++, |
| 102 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 103 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
| 104 | #endif |
| 105 | |
Nico Huber | 593e7de | 2015-11-04 15:46:00 +0100 | [diff] [blame] | 106 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 107 | /* Required for SandyBridge sighting 3715511 */ |
| 108 | bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); |
| 109 | bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); |
| 110 | } |
Nico Huber | bb9469c | 2015-10-21 11:49:23 +0200 | [diff] [blame] | 111 | |
| 112 | /* Reserve IOMMU BARs */ |
| 113 | const u32 capid0_a = pci_read_config32(dev, 0xe4); |
| 114 | if (!(capid0_a & (1 << 23))) { |
| 115 | mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4); |
| 116 | mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4); |
| 117 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 118 | } |
| 119 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 120 | static void pci_domain_set_resources(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 121 | { |
| 122 | uint64_t tom, me_base, touud; |
| 123 | uint32_t tseg_base, uma_size, tolud; |
| 124 | uint16_t ggc; |
| 125 | unsigned long long tomk; |
| 126 | |
| 127 | /* Total Memory 2GB example: |
| 128 | * |
| 129 | * 00000000 0000MB-1992MB 1992MB RAM (writeback) |
| 130 | * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) |
| 131 | * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) |
| 132 | * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) |
| 133 | * 7f200000 2034MB TOLUD |
| 134 | * 7f800000 2040MB MEBASE |
| 135 | * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) |
| 136 | * 80000000 2048MB TOM |
| 137 | * 100000000 4096MB-4102MB 6MB RAM (writeback) |
| 138 | * |
| 139 | * Total Memory 4GB example: |
| 140 | * |
| 141 | * 00000000 0000MB-2768MB 2768MB RAM (writeback) |
| 142 | * ad000000 2768MB-2776MB 8MB TSEG (SMRR) |
| 143 | * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) |
| 144 | * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) |
| 145 | * afa00000 2810MB TOLUD |
| 146 | * ff800000 4088MB MEBASE |
| 147 | * ff800000 4088MB-4096MB 8MB ME UMA (uncached) |
| 148 | * 100000000 4096MB TOM |
| 149 | * 100000000 4096MB-5374MB 1278MB RAM (writeback) |
| 150 | * 14fe00000 5368MB TOUUD |
| 151 | */ |
| 152 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 153 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 154 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 155 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 156 | touud = pci_read_config32(mch, TOUUD+4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 157 | touud <<= 32; |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 158 | touud |= pci_read_config32(mch, TOUUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 159 | |
| 160 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 161 | tolud = pci_read_config32(mch, TOLUD); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 162 | |
| 163 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 164 | tom = pci_read_config32(mch, 0xa4); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 165 | tom <<= 32; |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 166 | tom |= pci_read_config32(mch, 0xa0); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 167 | |
| 168 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 169 | touud, tolud, tom); |
| 170 | |
| 171 | /* ME UMA needs excluding if total memory <4GB */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 172 | me_base = pci_read_config32(mch, 0x74); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 173 | me_base <<= 32; |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 174 | me_base |= pci_read_config32(mch, 0x70); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 175 | |
| 176 | printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); |
| 177 | |
Patrick Rudolph | 240766a | 2015-10-15 15:33:25 +0200 | [diff] [blame] | 178 | uma_memory_base = tolud; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 179 | tomk = tolud >> 10; |
| 180 | if (me_base == tolud) { |
| 181 | /* ME is from MEBASE-TOM */ |
| 182 | uma_size = (tom - me_base) >> 10; |
| 183 | /* Increment TOLUD to account for ME as RAM */ |
| 184 | tolud += uma_size << 10; |
| 185 | /* UMA starts at old TOLUD */ |
| 186 | uma_memory_base = tomk * 1024ULL; |
| 187 | uma_memory_size = uma_size * 1024ULL; |
| 188 | printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", |
| 189 | me_base, uma_size >> 10); |
| 190 | } |
| 191 | |
| 192 | /* Graphics memory comes next */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 193 | ggc = pci_read_config16(mch, GGC); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 194 | if (!(ggc & 2)) { |
| 195 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 196 | |
| 197 | /* Graphics memory */ |
| 198 | uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; |
| 199 | printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); |
| 200 | tomk -= uma_size; |
| 201 | uma_memory_base = tomk * 1024ULL; |
| 202 | uma_memory_size += uma_size * 1024ULL; |
| 203 | |
| 204 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 205 | uma_size = ((ggc >> 8) & 0x3) * 1024ULL; |
| 206 | tomk -= uma_size; |
| 207 | uma_memory_base = tomk * 1024ULL; |
| 208 | uma_memory_size += uma_size * 1024ULL; |
| 209 | printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); |
| 210 | } |
| 211 | |
| 212 | /* Calculate TSEG size from its base which must be below GTT */ |
Arthur Heymans | 1704120 | 2018-06-26 21:06:25 +0200 | [diff] [blame] | 213 | tseg_base = pci_read_config32(mch, 0xb8); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 214 | uma_size = (uma_memory_base - tseg_base) >> 10; |
| 215 | tomk -= uma_size; |
| 216 | uma_memory_base = tomk * 1024ULL; |
| 217 | uma_memory_size += uma_size * 1024ULL; |
| 218 | printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", |
| 219 | tseg_base, uma_size >> 10); |
| 220 | |
| 221 | printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); |
| 222 | |
| 223 | /* Report the memory regions */ |
| 224 | ram_resource(dev, 3, 0, legacy_hole_base_k); |
| 225 | ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, |
| 226 | (tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
| 227 | |
| 228 | /* |
| 229 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 230 | * is remapped above TOM, TOUUD will account for both |
| 231 | */ |
| 232 | touud >>= 10; /* Convert to KB */ |
| 233 | if (touud > 4096 * 1024) { |
| 234 | ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); |
| 235 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
| 236 | (touud >> 10) - 4096); |
| 237 | } |
| 238 | |
| 239 | add_fixed_resources(dev, 6); |
| 240 | |
| 241 | assign_resources(dev->link_list); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 242 | } |
| 243 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 244 | static const char *northbridge_acpi_name(const struct device *dev) |
Patrick Rudolph | 3e47fc9 | 2017-06-07 09:44:07 +0200 | [diff] [blame] | 245 | { |
| 246 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 247 | return "PCI0"; |
| 248 | |
| 249 | if (dev->path.type != DEVICE_PATH_PCI) |
| 250 | return NULL; |
| 251 | |
| 252 | switch (dev->path.pci.devfn) { |
| 253 | case PCI_DEVFN(0, 0): |
| 254 | return "MCHC"; |
| 255 | } |
| 256 | |
| 257 | return NULL; |
| 258 | } |
| 259 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 260 | /* TODO We could determine how many PCIe busses we need in |
| 261 | * the bar. For now that number is hardcoded to a max of 64. |
| 262 | * See e7525/northbridge.c for an example. |
| 263 | */ |
| 264 | static struct device_operations pci_domain_ops = { |
| 265 | .read_resources = pci_domain_read_resources, |
| 266 | .set_resources = pci_domain_set_resources, |
| 267 | .enable_resources = NULL, |
| 268 | .init = NULL, |
| 269 | .scan_bus = pci_domain_scan_bus, |
Nico Huber | 9d9ce0d | 2015-10-26 12:59:49 +0100 | [diff] [blame] | 270 | .write_acpi_tables = northbridge_write_acpi_tables, |
Patrick Rudolph | 3e47fc9 | 2017-06-07 09:44:07 +0200 | [diff] [blame] | 271 | .acpi_name = northbridge_acpi_name, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 272 | }; |
| 273 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 274 | static void mc_read_resources(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 275 | { |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 276 | u32 pcie_config_base; |
| 277 | int buses; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 278 | |
| 279 | pci_dev_read_resources(dev); |
| 280 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 281 | buses = get_pcie_bar(&pcie_config_base); |
| 282 | if (buses) { |
Kyösti Mälkki | 27198ac | 2016-12-02 14:38:13 +0200 | [diff] [blame] | 283 | struct resource *resource = new_resource(dev, PCIEXBAR); |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 284 | mmconf_resource_init(resource, pcie_config_base, buses); |
| 285 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 286 | } |
| 287 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 288 | static void northbridge_dmi_init(struct device *dev) |
| 289 | { |
| 290 | u32 reg32; |
| 291 | |
| 292 | /* Clear error status bits */ |
| 293 | DMIBAR32(0x1c4) = 0xffffffff; |
| 294 | DMIBAR32(0x1d0) = 0xffffffff; |
| 295 | |
| 296 | /* Steps prior to DMI ASPM */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 297 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 298 | reg32 = DMIBAR32(0x250); |
| 299 | reg32 &= ~((1 << 22)|(1 << 20)); |
| 300 | reg32 |= (1 << 21); |
| 301 | DMIBAR32(0x250) = reg32; |
| 302 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 303 | |
| 304 | reg32 = DMIBAR32(0x238); |
| 305 | reg32 |= (1 << 29); |
| 306 | DMIBAR32(0x238) = reg32; |
| 307 | |
| 308 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 309 | reg32 = DMIBAR32(0x1f8); |
| 310 | reg32 |= (1 << 16); |
| 311 | DMIBAR32(0x1f8) = reg32; |
| 312 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 313 | reg32 = DMIBAR32(0x1f8); |
| 314 | reg32 &= ~(1 << 26); |
| 315 | reg32 |= (1 << 16); |
| 316 | DMIBAR32(0x1f8) = reg32; |
| 317 | |
| 318 | reg32 = DMIBAR32(0x1fc); |
| 319 | reg32 |= (1 << 12) | (1 << 23); |
| 320 | DMIBAR32(0x1fc) = reg32; |
| 321 | } |
| 322 | |
| 323 | /* Enable ASPM on SNB link, should happen before PCH link */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 324 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 325 | reg32 = DMIBAR32(0xd04); |
| 326 | reg32 |= (1 << 4); |
| 327 | DMIBAR32(0xd04) = reg32; |
| 328 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 329 | |
| 330 | reg32 = DMIBAR32(0x88); |
| 331 | reg32 |= (1 << 1) | (1 << 0); |
| 332 | DMIBAR32(0x88) = reg32; |
| 333 | } |
| 334 | |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 335 | /* Disable unused PEG devices based on devicetree */ |
| 336 | static void disable_peg(void) |
| 337 | { |
| 338 | struct device *dev; |
| 339 | u32 reg; |
| 340 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 341 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 342 | reg = pci_read_config32(dev, DEVEN); |
| 343 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 344 | dev = pcidev_on_root(1, 2); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 345 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 346 | printk(BIOS_DEBUG, "Disabling PEG12.\n"); |
| 347 | reg &= ~DEVEN_PEG12; |
| 348 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 349 | dev = pcidev_on_root(1, 1); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 350 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 351 | printk(BIOS_DEBUG, "Disabling PEG11.\n"); |
| 352 | reg &= ~DEVEN_PEG11; |
| 353 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 354 | dev = pcidev_on_root(1, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 355 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 356 | printk(BIOS_DEBUG, "Disabling PEG10.\n"); |
| 357 | reg &= ~DEVEN_PEG10; |
| 358 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 359 | dev = pcidev_on_root(2, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 360 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 361 | printk(BIOS_DEBUG, "Disabling IGD.\n"); |
| 362 | reg &= ~DEVEN_IGD; |
| 363 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 364 | dev = pcidev_on_root(4, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 365 | if (!dev || !dev->enabled) { |
| 366 | printk(BIOS_DEBUG, "Disabling Device 4.\n"); |
| 367 | reg &= ~DEVEN_D4EN; |
| 368 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 369 | dev = pcidev_on_root(6, 0); |
Nico Huber | 2dc15e9 | 2016-02-04 18:59:48 +0100 | [diff] [blame] | 370 | if (!dev || !dev->enabled) { |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 371 | printk(BIOS_DEBUG, "Disabling PEG60.\n"); |
| 372 | reg &= ~DEVEN_PEG60; |
| 373 | } |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 374 | dev = pcidev_on_root(7, 0); |
Patrick Rudolph | ecd4be8 | 2017-05-14 12:40:50 +0200 | [diff] [blame] | 375 | if (!dev || !dev->enabled) { |
| 376 | printk(BIOS_DEBUG, "Disabling Device 7.\n"); |
| 377 | reg &= ~DEVEN_D7EN; |
| 378 | } |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 379 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 380 | dev = pcidev_on_root(0, 0); |
Patrick Rudolph | 3660c0f | 2015-07-28 08:01:02 +0200 | [diff] [blame] | 381 | pci_write_config32(dev, DEVEN, reg); |
| 382 | if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { |
| 383 | /* Set the PEG clock gating bit. |
| 384 | * Disables the IO clock on all PEG devices. */ |
| 385 | MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; |
| 386 | printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); |
| 387 | } |
| 388 | } |
| 389 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 390 | static void northbridge_init(struct device *dev) |
| 391 | { |
| 392 | u8 bios_reset_cpl; |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 393 | u32 bridge_type; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 394 | |
| 395 | northbridge_dmi_init(dev); |
| 396 | |
Duncan Laurie | fe7b5d2 | 2012-06-23 20:14:07 -0700 | [diff] [blame] | 397 | bridge_type = MCHBAR32(0x5f10); |
| 398 | bridge_type &= ~0xff; |
| 399 | |
| 400 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 401 | /* Enable Power Aware Interrupt Routing */ |
| 402 | u8 pair = MCHBAR8(0x5418); |
| 403 | pair &= ~0xf; /* Clear 3:0 */ |
| 404 | pair |= 0x4; /* Fixed Priority */ |
| 405 | MCHBAR8(0x5418) = pair; |
| 406 | |
| 407 | /* 30h for IvyBridge */ |
| 408 | bridge_type |= 0x30; |
| 409 | } else { |
| 410 | /* 20h for Sandybridge */ |
| 411 | bridge_type |= 0x20; |
| 412 | } |
| 413 | MCHBAR32(0x5f10) = bridge_type; |
| 414 | |
Patrick Rudolph | aad34cd | 2015-10-21 18:05:01 +0200 | [diff] [blame] | 415 | /* Turn off unused devices. Has to be done before |
| 416 | * setting BIOS_RESET_CPL. |
| 417 | */ |
| 418 | disable_peg(); |
| 419 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 420 | /* |
| 421 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 422 | * that BIOS has initialized memory and power management |
| 423 | */ |
| 424 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 425 | bios_reset_cpl |= 1; |
| 426 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 427 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 428 | |
| 429 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 430 | mdelay(1); |
| 431 | set_power_limits(28); |
| 432 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 433 | /* |
| 434 | * CPUs with configurable TDP also need power limits set |
| 435 | * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. |
| 436 | */ |
| 437 | if (cpu_config_tdp_levels()) { |
| 438 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
| 439 | MCHBAR32(0x59A0) = msr.lo; |
| 440 | MCHBAR32(0x59A4) = msr.hi; |
| 441 | } |
| 442 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 443 | /* Set here before graphics PM init */ |
| 444 | MCHBAR32(0x5500) = 0x00100001; |
| 445 | } |
| 446 | |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 447 | void northbridge_write_smram(u8 smram) |
| 448 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 449 | pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); |
Vladimir Serbinenko | c16e9dfa | 2015-05-29 16:18:01 +0200 | [diff] [blame] | 450 | } |
| 451 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 452 | static struct pci_operations intel_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 453 | .set_subsystem = pci_dev_set_subsystem, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 454 | }; |
| 455 | |
| 456 | static struct device_operations mc_ops = { |
| 457 | .read_resources = mc_read_resources, |
Kyösti Mälkki | 27198ac | 2016-12-02 14:38:13 +0200 | [diff] [blame] | 458 | .set_resources = pci_dev_set_resources, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 459 | .enable_resources = pci_dev_enable_resources, |
| 460 | .init = northbridge_init, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 461 | .scan_bus = 0, |
| 462 | .ops_pci = &intel_pci_ops, |
Vladimir Serbinenko | 0a66991 | 2014-10-05 14:34:17 +0200 | [diff] [blame] | 463 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 464 | }; |
| 465 | |
Walter Murphy | 496f4a0 | 2012-04-23 11:08:03 -0700 | [diff] [blame] | 466 | static const struct pci_driver mc_driver_0100 __pci_driver = { |
| 467 | .ops = &mc_ops, |
| 468 | .vendor = PCI_VENDOR_ID_INTEL, |
| 469 | .device = 0x0100, |
| 470 | }; |
| 471 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 472 | static const struct pci_driver mc_driver __pci_driver = { |
| 473 | .ops = &mc_ops, |
| 474 | .vendor = PCI_VENDOR_ID_INTEL, |
| 475 | .device = 0x0104, /* Sandy bridge */ |
| 476 | }; |
| 477 | |
Damien Zammit | 3517038 | 2014-10-29 00:11:53 +1100 | [diff] [blame] | 478 | static const struct pci_driver mc_driver_150 __pci_driver = { |
| 479 | .ops = &mc_ops, |
| 480 | .vendor = PCI_VENDOR_ID_INTEL, |
| 481 | .device = 0x0150, /* Ivy bridge */ |
| 482 | }; |
| 483 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 484 | static const struct pci_driver mc_driver_1 __pci_driver = { |
| 485 | .ops = &mc_ops, |
| 486 | .vendor = PCI_VENDOR_ID_INTEL, |
| 487 | .device = 0x0154, /* Ivy bridge */ |
| 488 | }; |
| 489 | |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 490 | static const struct pci_driver mc_driver_158 __pci_driver = { |
| 491 | .ops = &mc_ops, |
| 492 | .vendor = PCI_VENDOR_ID_INTEL, |
| 493 | .device = 0x0158, /* Ivy bridge */ |
| 494 | }; |
| 495 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 496 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 497 | .read_resources = DEVICE_NOOP, |
| 498 | .set_resources = DEVICE_NOOP, |
| 499 | .enable_resources = DEVICE_NOOP, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 500 | .init = mp_cpu_bus_init, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 501 | .scan_bus = 0, |
| 502 | }; |
| 503 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 504 | static void enable_dev(struct device *dev) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 505 | { |
| 506 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 507 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 508 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 509 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 510 | dev->ops = &cpu_bus_ops; |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | struct chip_operations northbridge_intel_sandybridge_ops = { |
Damien Zammit | 3517038 | 2014-10-29 00:11:53 +1100 | [diff] [blame] | 515 | CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 516 | .enable_dev = enable_dev, |
| 517 | }; |