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Macpaul Lin5d16f8d2022-08-11 16:27:10 +08001/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
Yidi Lin24ea3f32021-01-07 20:25:54 +08002
Rex-BC Chen61be50d2021-08-10 12:39:32 +08003#include <bootmem.h>
Yu-Ping Wu3b9d6a42022-07-19 17:09:39 +08004#include <console/console.h>
Yidi Lin24ea3f32021-01-07 20:25:54 +08005#include <device/device.h>
Jianjun Wangb4a71222021-07-14 15:41:20 +08006#include <device/pci.h>
Flora Fu5cd18712021-06-25 23:27:56 +08007#include <soc/apusys.h>
Nina Wuc25aa5b2021-06-21 09:13:19 +08008#include <soc/devapc.h>
Rex-BC Chen61be50d2021-08-10 12:39:32 +08009#include <soc/dfd.h>
Yidi Lin24ea3f32021-01-07 20:25:54 +080010#include <soc/emi.h>
Rex-BC Chen8316db22021-08-13 16:34:26 +080011#include <soc/hdmi.h>
alex.miao4a2887f2021-05-17 21:58:55 +080012#include <soc/mcupm.h>
Yidi Lin27be9042021-03-25 17:50:14 +080013#include <soc/mmu_operations.h>
Jianjun Wangb4a71222021-07-14 15:41:20 +080014#include <soc/pcie.h>
Rex-BC Chenab2cbf72021-05-03 20:44:09 +080015#include <soc/sspm.h>
Yidi Linbe8621d2021-04-19 16:06:55 +080016#include <soc/ufs.h>
Yidi Lin24ea3f32021-01-07 20:25:54 +080017#include <symbols.h>
18
Rex-BC Chen61be50d2021-08-10 12:39:32 +080019void bootmem_platform_add_ranges(void)
20{
21 if (CONFIG(MTK_DFD))
22 bootmem_add_range(DFD_DUMP_ADDRESS, DFD_DUMP_SIZE, BM_MEM_RESERVED);
23}
24
Yidi Lin24ea3f32021-01-07 20:25:54 +080025static void soc_read_resources(struct device *dev)
26{
Kyösti Mälkki85eb34e2022-06-20 14:13:36 +030027 ram_range(dev, 0, (uintptr_t)_dram, sdram_size());
Yidi Lin24ea3f32021-01-07 20:25:54 +080028}
29
30static void soc_init(struct device *dev)
31{
Yidi Lin27be9042021-03-25 17:50:14 +080032 mtk_mmu_disable_l2c_sram();
Nina Wuc25aa5b2021-06-21 09:13:19 +080033 dapc_init();
Flora Fu5cd18712021-06-25 23:27:56 +080034 apusys_init();
alex.miao4a2887f2021-05-17 21:58:55 +080035 mcupm_init();
Rex-BC Chenab2cbf72021-05-03 20:44:09 +080036 sspm_init();
Rex-BC Chen61be50d2021-08-10 12:39:32 +080037
38 if (CONFIG(MTK_DFD))
39 dfd_init();
40
Yidi Linbe8621d2021-04-19 16:06:55 +080041 ufs_disable_refclk();
Rex-BC Chen8316db22021-08-13 16:34:26 +080042 hdmi_low_power_setting();
Yidi Lin24ea3f32021-01-07 20:25:54 +080043}
44
45static struct device_operations soc_ops = {
46 .read_resources = soc_read_resources,
Yu-Ping Wu39e6f852022-03-14 16:53:59 +080047 .set_resources = noop_set_resources,
Yidi Lin24ea3f32021-01-07 20:25:54 +080048 .init = soc_init,
49};
50
Jianjun Wangb4a71222021-07-14 15:41:20 +080051static struct device_operations pci_domain_ops = {
52 .read_resources = &mtk_pcie_domain_read_resources,
53 .set_resources = &mtk_pcie_domain_set_resources,
54 .scan_bus = &pci_domain_scan_bus,
55 .enable = &mtk_pcie_domain_enable,
56};
57
Yidi Lin24ea3f32021-01-07 20:25:54 +080058static void enable_soc_dev(struct device *dev)
59{
Jianjun Wangb4a71222021-07-14 15:41:20 +080060 if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
61 dev->ops = &soc_ops;
Yu-Ping Wu3b9d6a42022-07-19 17:09:39 +080062 else if (dev->path.type == DEVICE_PATH_DOMAIN) {
63 if (mainboard_needs_pcie_init())
64 dev->ops = &pci_domain_ops;
65 else
66 printk(BIOS_DEBUG, "Skip setting PCIe ops\n");
67 }
Yidi Lin24ea3f32021-01-07 20:25:54 +080068}
69
70struct chip_operations soc_mediatek_mt8195_ops = {
71 CHIP_NAME("SOC Mediatek MT8195")
72 .enable_dev = enable_soc_dev,
73};