| commit | 990555b0efafa2860888eeb335477720f464acb2 | [log] [tgz] |
|---|---|---|
| author | Duncan Laurie <dlaurie@chromium.org> | Fri May 10 11:00:07 2013 -0700 |
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | Sun Nov 24 16:11:30 2013 +0100 |
| tree | 2140f74fdcee4f078d824e2997336b8a114533e5 | |
| parent | fd0bc14844d7ef96781404e4d0a14e522e4f5827 [diff] [blame] |
haswell: Update GT PM register value This was changed to 0x80000000 in SA BWG 1.5.0. Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50852 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4166 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index e577fb5..f3ddbd3 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c
@@ -124,7 +124,7 @@ gtt_write(0x12054, 0x0000000a); gtt_write(0x22054, 0x0000000a); - gtt_write(0x0a008, 0x10000000); + gtt_write(0x0a008, 0x80000000); gtt_write(0x0a024, 0x00000b92); /* Enable RC6 in idle */