Zhuohao Lee | 11f0160 | 2018-08-02 23:59:16 +0800 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_B" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 19 | register "gen1_dec" = "0x00fc0801" |
| 20 | register "gen2_dec" = "0x000c0201" |
| 21 | # EC memory map range is 0x900-0x9ff |
| 22 | register "gen3_dec" = "0x00fc0901" |
| 23 | |
| 24 | # Enable DPTF |
| 25 | register "dptf_enable" = "1" |
| 26 | |
| 27 | # Enable S0ix |
| 28 | register "s0ix_enable" = "1" |
| 29 | |
marxwang | 5b56565 | 2018-09-11 12:08:23 +0800 | [diff] [blame^] | 30 | # Disable Command TriState |
| 31 | register "CmdTriStateDis" = "1" |
| 32 | |
Zhuohao Lee | 11f0160 | 2018-08-02 23:59:16 +0800 | [diff] [blame] | 33 | # FSP Configuration |
| 34 | register "ProbelessTrace" = "0" |
| 35 | register "EnableLan" = "0" |
| 36 | register "EnableSata" = "0" |
| 37 | register "SataSalpSupport" = "0" |
| 38 | register "SataMode" = "0" |
| 39 | register "SataPortsEnable[0]" = "0" |
| 40 | register "EnableAzalia" = "1" |
| 41 | register "DspEnable" = "1" |
| 42 | register "IoBufferOwnership" = "3" |
| 43 | register "EnableTraceHub" = "0" |
| 44 | register "SsicPortEnable" = "0" |
| 45 | register "SmbusEnable" = "1" |
Zhuohao Lee | fa61f5a | 2018-09-08 16:53:10 +0800 | [diff] [blame] | 46 | register "Cio2Enable" = "0" |
| 47 | register "SaImguEnable" = "0" |
Zhuohao Lee | 11f0160 | 2018-08-02 23:59:16 +0800 | [diff] [blame] | 48 | register "ScsEmmcEnabled" = "1" |
| 49 | register "ScsEmmcHs400Enabled" = "1" |
| 50 | register "ScsSdCardEnabled" = "2" |
| 51 | register "PttSwitch" = "0" |
| 52 | register "InternalGfx" = "1" |
| 53 | register "SkipExtGfxScan" = "1" |
| 54 | register "Device4Enable" = "1" |
| 55 | register "HeciEnabled" = "0" |
| 56 | register "SaGv" = "3" |
| 57 | register "SerialIrqConfigSirqEnable" = "1" |
| 58 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 59 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 60 | register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| 61 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 62 | register "PmTimerDisabled" = "1" |
| 63 | register "VmxEnable" = "1" |
| 64 | |
| 65 | register "pirqa_routing" = "PCH_IRQ11" |
| 66 | register "pirqb_routing" = "PCH_IRQ10" |
| 67 | register "pirqc_routing" = "PCH_IRQ11" |
| 68 | register "pirqd_routing" = "PCH_IRQ11" |
| 69 | register "pirqe_routing" = "PCH_IRQ11" |
| 70 | register "pirqf_routing" = "PCH_IRQ11" |
| 71 | register "pirqg_routing" = "PCH_IRQ11" |
| 72 | register "pirqh_routing" = "PCH_IRQ11" |
| 73 | |
| 74 | # VR Settings Configuration for 4 Domains |
| 75 | #+----------------+-------+-------+-------+-------+ |
| 76 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 77 | #+----------------+-------+-------+-------+-------+ |
| 78 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 79 | #| Psi2Threshold | 2A | 2A | 2A | 2A | |
| 80 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 81 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 82 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 83 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 84 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 85 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 86 | #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | |
| 87 | #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | |
| 88 | #+----------------+-------+-------+-------+-------+ |
| 89 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 90 | .vr_config_enable = 1, |
| 91 | .psi1threshold = VR_CFG_AMP(20), |
| 92 | .psi2threshold = VR_CFG_AMP(2), |
| 93 | .psi3threshold = VR_CFG_AMP(1), |
| 94 | .psi3enable = 1, |
| 95 | .psi4enable = 1, |
| 96 | .imon_slope = 0x0, |
| 97 | .imon_offset = 0x0, |
| 98 | .voltage_limit = 1520, |
| 99 | .ac_loadline = 1500, |
| 100 | .dc_loadline = 1430, |
| 101 | }" |
| 102 | |
| 103 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 104 | .vr_config_enable = 1, |
| 105 | .psi1threshold = VR_CFG_AMP(20), |
| 106 | .psi2threshold = VR_CFG_AMP(2), |
| 107 | .psi3threshold = VR_CFG_AMP(1), |
| 108 | .psi3enable = 1, |
| 109 | .psi4enable = 1, |
| 110 | .imon_slope = 0x0, |
| 111 | .imon_offset = 0x0, |
| 112 | .voltage_limit = 1520, |
| 113 | .ac_loadline = 570, |
| 114 | .dc_loadline = 483, |
| 115 | }" |
| 116 | |
| 117 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 118 | .vr_config_enable = 1, |
| 119 | .psi1threshold = VR_CFG_AMP(20), |
| 120 | .psi2threshold = VR_CFG_AMP(2), |
| 121 | .psi3threshold = VR_CFG_AMP(1), |
| 122 | .psi3enable = 1, |
| 123 | .psi4enable = 1, |
| 124 | .imon_slope = 0x0, |
| 125 | .imon_offset = 0x0, |
| 126 | .voltage_limit = 1520, |
| 127 | .ac_loadline = 550, |
| 128 | .dc_loadline = 420, |
| 129 | }" |
| 130 | |
| 131 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 132 | .vr_config_enable = 1, |
| 133 | .psi1threshold = VR_CFG_AMP(20), |
| 134 | .psi2threshold = VR_CFG_AMP(2), |
| 135 | .psi3threshold = VR_CFG_AMP(1), |
| 136 | .psi3enable = 1, |
| 137 | .psi4enable = 1, |
| 138 | .imon_slope = 0x0, |
| 139 | .imon_offset = 0x0, |
| 140 | .voltage_limit = 1520, |
| 141 | .ac_loadline = 550, |
| 142 | .dc_loadline = 420, |
| 143 | }" |
| 144 | |
| 145 | # Enable Root port 1. |
| 146 | register "PcieRpEnable[0]" = "1" |
| 147 | # Enable CLKREQ# |
| 148 | register "PcieRpClkReqSupport[0]" = "1" |
| 149 | # RP 1 uses SRCCLKREQ1# |
| 150 | register "PcieRpClkReqNumber[0]" = "1" |
| 151 | # RP 1 uses uses CLK SRC 1 |
| 152 | register "PcieRpClkSrcNumber[0]" = "1" |
| 153 | # RP 1, Enable Advanced Error Reporting |
| 154 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 155 | # RP 1, Enable Latency Tolerance Reporting Mechanism |
| 156 | register "PcieRpLtrEnable[0]" = "1" |
| 157 | |
| 158 | register "usb2_ports[0]" = "USB2_PORT_SHORT(OC0)" # Type-C Port 1 |
| 159 | register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-A Port |
| 160 | register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth |
| 161 | register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 |
| 162 | register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 |
| 163 | register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera |
| 164 | |
| 165 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 |
| 166 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 |
| 167 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port |
| 168 | register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty |
| 169 | |
| 170 | # Intel Common SoC Config |
| 171 | #+-------------------+---------------------------+ |
| 172 | #| Field | Value | |
| 173 | #+-------------------+---------------------------+ |
| 174 | #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | |
| 175 | #| I2C0 | Touchscreen | |
| 176 | #| I2C1 | Trackpad | |
| 177 | #| I2C5 | Audio | |
| 178 | #+-------------------+---------------------------+ |
| 179 | register "common_soc_config" = "{ |
| 180 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 181 | .i2c[0] = { |
| 182 | .speed = I2C_SPEED_FAST, |
| 183 | .speed_config[0] = { |
| 184 | .speed = I2C_SPEED_FAST, |
| 185 | .scl_lcnt = 190, |
| 186 | .scl_hcnt = 100, |
| 187 | .sda_hold = 36, |
| 188 | }, |
| 189 | }, |
| 190 | .i2c[1] = { |
| 191 | .speed = I2C_SPEED_FAST, |
| 192 | .speed_config[0] = { |
| 193 | .speed = I2C_SPEED_FAST, |
| 194 | .scl_lcnt = 190, |
| 195 | .scl_hcnt = 100, |
| 196 | .sda_hold = 36, |
| 197 | }, |
| 198 | .early_init = 1, |
| 199 | }, |
| 200 | .i2c[5] = { |
| 201 | .speed = I2C_SPEED_FAST, |
| 202 | .speed_config[0] = { |
| 203 | .speed = I2C_SPEED_FAST, |
| 204 | .scl_lcnt = 190, |
| 205 | .scl_hcnt = 100, |
| 206 | .sda_hold = 36, |
| 207 | }, |
| 208 | }, |
kane_chen | e781856 | 2018-08-31 17:38:07 +0800 | [diff] [blame] | 209 | .gspi[0] = { |
| 210 | .speed_mhz = 1, |
| 211 | .early_init = 1, |
| 212 | }, |
Zhuohao Lee | 11f0160 | 2018-08-02 23:59:16 +0800 | [diff] [blame] | 213 | }" |
| 214 | |
| 215 | # Touchscreen |
| 216 | register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| 217 | |
| 218 | # Trackpad |
| 219 | register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" |
| 220 | |
| 221 | # Audio |
| 222 | register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" |
| 223 | |
| 224 | # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| 225 | register "SerialIoDevMode" = "{ |
| 226 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 227 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 228 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 229 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 230 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 231 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 232 | [PchSerialIoIndexSpi0] = PchSerialIoPci, |
| 233 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 234 | [PchSerialIoIndexUart0] = PchSerialIoPci, |
| 235 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 236 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| 237 | }" |
| 238 | |
| 239 | register "speed_shift_enable" = "1" |
| 240 | register "psys_pmax" = "45" |
| 241 | # PL2 override 18W for AML-Y |
| 242 | register "tdp_pl2_override" = "18" |
| 243 | register "tcc_offset" = "10" # TCC of 90C |
| 244 | |
| 245 | # Use default SD card detect GPIO configuration |
| 246 | register "sdcard_cd_gpio_default" = "GPP_E15" |
| 247 | |
| 248 | # PCH Trip Temperature in degree C |
| 249 | register "pch_trip_temp" = "75" |
| 250 | |
| 251 | device cpu_cluster 0 on |
| 252 | device lapic 0 on end |
| 253 | end |
| 254 | device domain 0 on |
| 255 | device pci 00.0 on end # Host Bridge |
| 256 | device pci 02.0 on end # Integrated Graphics Device |
| 257 | device pci 14.0 on end # USB xHCI |
| 258 | device pci 14.1 on end # USB xDCI (OTG) |
| 259 | device pci 14.2 on end # Thermal Subsystem |
| 260 | device pci 15.0 on end # I2C #0 |
| 261 | device pci 15.1 on |
| 262 | chip drivers/i2c/generic |
| 263 | register "hid" = ""ELAN0000"" |
| 264 | register "desc" = ""ELAN Touchpad"" |
| 265 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" |
| 266 | register "wake" = "GPE0_DW0_05" # GPP_B5 |
| 267 | device i2c 15 on end |
| 268 | end |
| 269 | end # I2C #1 |
| 270 | device pci 15.2 off end # I2C #2 |
| 271 | device pci 15.3 off end # I2C #3 |
| 272 | device pci 16.0 on end # Management Engine Interface 1 |
| 273 | device pci 16.1 off end # Management Engine Interface 2 |
| 274 | device pci 16.2 off end # Management Engine IDE-R |
| 275 | device pci 16.3 off end # Management Engine KT Redirection |
| 276 | device pci 16.4 off end # Management Engine Interface 3 |
| 277 | device pci 17.0 off end # SATA |
| 278 | device pci 19.0 on end # UART #2 |
| 279 | device pci 19.1 on |
| 280 | chip drivers/i2c/max98927 |
| 281 | register "interleave_mode" = "1" |
| 282 | register "vmon_slot_no" = "4" |
| 283 | register "imon_slot_no" = "5" |
| 284 | register "uid" = "0" |
| 285 | register "desc" = ""SSM4567 Right Speaker Amp"" |
| 286 | register "name" = ""MAXR"" |
| 287 | device i2c 39 on end |
| 288 | end |
| 289 | chip drivers/i2c/max98927 |
| 290 | register "interleave_mode" = "1" |
| 291 | register "vmon_slot_no" = "6" |
| 292 | register "imon_slot_no" = "7" |
| 293 | register "uid" = "1" |
| 294 | register "desc" = ""SSM4567 Left Speaker Amp"" |
| 295 | register "name" = ""MAXL"" |
| 296 | device i2c 3A on end |
| 297 | end |
marxwang | 3b8ef2b | 2018-09-07 13:42:00 +0800 | [diff] [blame] | 298 | chip drivers/i2c/da7219 |
| 299 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" |
| 300 | register "btn_cfg" = "50" |
| 301 | register "mic_det_thr" = "500" |
| 302 | register "jack_ins_deb" = "20" |
| 303 | register "jack_det_rate" = ""32ms_64ms"" |
| 304 | register "jack_rem_deb" = "1" |
| 305 | register "a_d_btn_thr" = "0xa" |
| 306 | register "d_b_btn_thr" = "0x16" |
| 307 | register "b_c_btn_thr" = "0x21" |
| 308 | register "c_mic_btn_thr" = "0x3e" |
| 309 | register "btn_avg" = "4" |
| 310 | register "adc_1bit_rpt" = "1" |
| 311 | register "micbias_lvl" = "2600" |
| 312 | register "mic_amp_in_sel" = ""diff"" |
| 313 | device i2c 1A on end |
| 314 | end |
Zhuohao Lee | 11f0160 | 2018-08-02 23:59:16 +0800 | [diff] [blame] | 315 | end # I2C #5 |
| 316 | device pci 19.2 off end # I2C #4 |
| 317 | device pci 1c.0 on |
| 318 | chip drivers/intel/wifi |
| 319 | register "wake" = "GPE0_DW0_00" # GPP_B0 |
| 320 | device pci 00.0 on end |
| 321 | end |
| 322 | end # PCI Express Port 1 |
| 323 | device pci 1c.1 off end # PCI Express Port 2 |
| 324 | device pci 1c.2 off end # PCI Express Port 3 |
| 325 | device pci 1c.3 off end # PCI Express Port 4 |
| 326 | device pci 1c.4 off end # PCI Express Port 5 |
| 327 | device pci 1c.5 off end # PCI Express Port 6 |
| 328 | device pci 1c.6 off end # PCI Express Port 7 |
| 329 | device pci 1c.7 off end # PCI Express Port 8 |
| 330 | device pci 1d.0 off end # PCI Express Port 9 |
| 331 | device pci 1d.1 off end # PCI Express Port 10 |
| 332 | device pci 1d.2 off end # PCI Express Port 11 |
| 333 | device pci 1d.3 off end # PCI Express Port 12 |
| 334 | device pci 1e.0 on end # UART #0 |
| 335 | device pci 1e.1 off end # UART #1 |
| 336 | device pci 1e.2 on |
| 337 | chip drivers/spi/acpi |
| 338 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 339 | register "compat_string" = ""google,cr50"" |
| 340 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| 341 | device spi 0 on end |
| 342 | end |
| 343 | end # GSPI #0 |
| 344 | device pci 1e.3 off end # GSPI #1 |
| 345 | device pci 1e.4 on end # eMMC |
| 346 | device pci 1e.5 off end # SDIO |
| 347 | device pci 1e.6 on end # SDCard |
| 348 | device pci 1f.0 on |
| 349 | chip ec/google/chromeec |
| 350 | device pnp 0c09.0 on end |
| 351 | end |
| 352 | end # LPC Interface |
| 353 | device pci 1f.1 on end # P2SB |
| 354 | device pci 1f.2 on end # Power Management Controller |
| 355 | device pci 1f.3 on end # Intel HDA |
| 356 | device pci 1f.4 on end # SMBus |
| 357 | device pci 1f.5 on end # PCH SPI |
| 358 | device pci 1f.6 off end # GbE |
| 359 | end |
| 360 | end |