Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 4 | ## |
| 5 | ## This program is free software; you can redistribute it and/or modify |
| 6 | ## it under the terms of the GNU General Public License as published by |
| 7 | ## the Free Software Foundation; either version 2 of the License, or |
| 8 | ## (at your option) any later version. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 16 | source "src/soc/intel/xeon_sp/skx/Kconfig" |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 17 | source "src/soc/intel/xeon_sp/cpx/Kconfig" |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 18 | |
| 19 | config XEON_SP_COMMON_BASE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 20 | bool |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 21 | |
| 22 | config SOC_INTEL_SKYLAKE_SP |
| 23 | bool |
| 24 | select XEON_SP_COMMON_BASE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 25 | help |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 26 | Intel Skylake-SP support |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 27 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 28 | config SOC_INTEL_COOPERLAKE_SP |
| 29 | bool |
| 30 | select XEON_SP_COMMON_BASE |
| 31 | help |
| 32 | Intel Cooperlake-SP support |
| 33 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 34 | if XEON_SP_COMMON_BASE |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 35 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 36 | config CPU_SPECIFIC_OPTIONS |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 37 | def_bool y |
| 38 | select ARCH_BOOTBLOCK_X86_32 |
| 39 | select ARCH_RAMSTAGE_X86_32 |
| 40 | select ARCH_ROMSTAGE_X86_32 |
| 41 | select ARCH_VERSTAGE_X86_32 |
| 42 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 43 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 44 | select POSTCAR_CONSOLE |
| 45 | select SOC_INTEL_COMMON |
| 46 | select SOC_INTEL_COMMON_RESET |
| 47 | select PLATFORM_USES_FSP2_0 |
| 48 | select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS |
| 49 | select FSP_T_XIP |
| 50 | select FSP_M_XIP |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 51 | select POSTCAR_STAGE |
| 52 | select IOAPIC |
| 53 | select PARALLEL_MP |
| 54 | select SMP |
| 55 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 56 | select COMMON_FADT |
| 57 | select SOC_INTEL_COMMON_BLOCK |
| 58 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 59 | select SOC_INTEL_COMMON_BLOCK_TIMER |
| 60 | select SOC_INTEL_COMMON_BLOCK_LPC |
| 61 | select SOC_INTEL_COMMON_BLOCK_RTC |
| 62 | select SOC_INTEL_COMMON_BLOCK_SPI |
| 63 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
| 64 | select SOC_INTEL_COMMON_BLOCK_PCR |
| 65 | select TSC_MONOTONIC_TIMER |
| 66 | select UDELAY_TSC |
| 67 | select SUPPORT_CPU_UCODE_IN_CBFS |
Nico Huber | 0266be0 | 2020-03-08 18:36:00 +0100 | [diff] [blame] | 68 | select MICROCODE_BLOB_NOT_HOOKED_UP |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 69 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 70 | select FSP_CAR |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 71 | |
| 72 | config MAINBOARD_USES_FSP2_0 |
| 73 | bool |
| 74 | default y |
| 75 | |
| 76 | config USE_FSP2_0_DRIVER |
| 77 | def_bool y |
| 78 | depends on MAINBOARD_USES_FSP2_0 |
| 79 | select PLATFORM_USES_FSP2_0 |
| 80 | select UDK_2015_BINDING |
| 81 | select POSTCAR_CONSOLE |
| 82 | select POSTCAR_STAGE |
| 83 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 84 | config MAX_SOCKET |
| 85 | int |
| 86 | default 2 |
| 87 | |
| 88 | # For 2S config, the number of cpus could be as high as |
| 89 | # 2 threads * 20 cores * 2 sockets |
| 90 | config MAX_CPUS |
| 91 | int |
| 92 | default 80 |
| 93 | |
| 94 | config PCR_BASE_ADDRESS |
| 95 | hex |
| 96 | default 0xfd000000 |
| 97 | help |
| 98 | This option allows you to select MMIO Base Address of sideband bus. |
| 99 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 100 | config DCACHE_BSP_STACK_SIZE |
| 101 | hex |
| 102 | default 0x10000 |
| 103 | |
| 104 | config MMCONF_BASE_ADDRESS |
| 105 | hex |
| 106 | default 0x80000000 |
| 107 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 108 | config C_ENV_BOOTBLOCK_SIZE |
| 109 | hex |
| 110 | default 0xC000 |
| 111 | |
| 112 | config HEAP_SIZE |
| 113 | hex |
| 114 | default 0x80000 |
| 115 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 116 | endif ## SOC_INTEL_XEON_SP |