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review.coreboot.org / coreboot / 5a62427e1451bb5e6e2c397b4c5950fac90cda1c / . / src / northbridge / intel / sandybridge / acpi / sandybridge.asl
blob: 0670c7b0a6a2ff6de5c7ff12ce3a848aca5ce1ca [file] [log] [blame]
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
Patrick Rudolph0b643d22017-07-05 20:07:06 +0200[diff] [blame]5 * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org>
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]16 */
17
Duncan Laurie55864ef2012-07-16 12:27:42 -0700[diff] [blame]18#include "hostbridge.asl"
Patrick Rudolph0b643d22017-07-05 20:07:06 +0200[diff] [blame]19#include "peg.asl"
Elyes HAOUAS4ec67fc2019-10-30 12:39:17 +0100[diff] [blame]20#include <southbridge/intel/common/rcba.h>
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]21
22/* PCI Device Resource Consumption */
23Device (PDRC)
24{
25 Name (_HID, EISAID("PNP0C02"))
26 Name (_UID, 1)
27
28 Name (PDRS, ResourceTemplate() {
Elyes HAOUAS4ec67fc2019-10-30 12:39:17 +0100[diff] [blame]29 Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
Patrick Rudolph2af2f2c2019-03-26 14:33:16 +0100[diff] [blame]30 // Filled by _CRS
31 Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB)
32 Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB)
33 Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB)
34 Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX)
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]35 Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Patrick Rudolph2af2f2c2019-03-26 14:33:16 +0100[diff] [blame]36 Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]37 Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
38
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]39#if CONFIG(CHROMEOS_RAMOOPS)
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]40 Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
41 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
42#endif
43
44 /* Required for SandyBridge sighting 3715511 */
45 Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
46 Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
47 })
48
49 // Current Resource Settings
50 Method (_CRS, 0, Serialized)
51 {
Patrick Rudolph2af2f2c2019-03-26 14:33:16 +0100[diff] [blame]52 CreateDwordField (PDRS, ^MCHB._BAS, MBR0)
53 MBR0 = \_SB.PCI0.MCHC.MHBR << 15
54
55 CreateDwordField (PDRS, ^DMIB._BAS, DBR0)
56 DBR0 = \_SB.PCI0.MCHC.DMBR << 12
57
58 CreateDwordField (PDRS, ^EGPB._BAS, EBR0)
59 EBR0 = \_SB.PCI0.MCHC.EPBR << 12
60
61 CreateDwordField (PDRS, ^PCIX._BAS, XBR0)
62 XBR0 = \_SB.PCI0.MCHC.PXBR << 26
63
64 CreateDwordField (PDRS, ^PCIX._LEN, XSZ0)
Patrick Rudolph5a624272020-02-11 16:02:11 +0100[diff] [blame^]65 XSZ0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ
Patrick Rudolph2af2f2c2019-03-26 14:33:16 +0100[diff] [blame]66
Stefan Reinauer00636b02012-04-04 00:08:51 +0200[diff] [blame]67 Return(PDRS)
68 }
69}
70
71// Integrated graphics 0:2.0
Nico Huber62047d12015-08-27 15:07:03 +0200[diff] [blame]72#include <drivers/intel/gma/acpi/pch.asl>