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review.coreboot.org / coreboot / 57686f848597f6b133c9d45a9b98a54638399b32 / . / src / cpu / amd / agesa / family14 / Kconfig
blob: dea839ea513edb54d8356789185e1ad27d81c93d [file] [log] [blame]
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]1#
2# This file is part of the coreboot project.
3#
4# Copyright (C) 2011 Advanced Micro Devices, Inc.
5#
6# This program is free software; you can redistribute it and/or modify
7# it under the terms of the GNU General Public License as published by
8# the Free Software Foundation; version 2 of the License.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
15# You should have received a copy of the GNU General Public License
16# along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +0100[diff] [blame]17# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]18#
19
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]20config CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]21 bool
22 select PCI_IO_CFG_EXT
Aaron Durbin57686f82013-03-20 15:50:59 -0500[diff] [blame^]23 select X86_AMD_FIXED_MTRRS
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]24
25config CPU_ADDR_BITS
26 int
27 default 36
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]28 depends on CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]29
30config CPU_SOCKET_TYPE
31 hex
32 default 0x10
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]33 depends on CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]34
35# DDR2 and REG
36config DIMM_SUPPORT
37 hex
38 default 0x0104
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]39 depends on CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]40
41config EXT_RT_TBL_SUPPORT
42 bool
43 default n
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]44 depends on CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]45
46config EXT_CONF_SUPPORT
47 bool
48 default n
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]49 depends on CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]50
51config CBB
52 hex
53 default 0x0
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]54 depends on CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]55
56config CDB
57 hex
58 default 0x18
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]59 depends on CPU_AMD_AGESA_FAMILY14
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]60
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]61config XIP_ROM_SIZE
62 hex
63 default 0x80000
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]64 depends on CPU_AMD_AGESA_FAMILY14
65
Frank Vibrans420faca2011-02-14 18:42:12 +0000[diff] [blame]66config HAVE_INIT_TIMER
67 bool
68 default y
efdesign9805a89ab2011-06-20 17:38:49 -0700[diff] [blame]69 depends on CPU_AMD_AGESA_FAMILY14
70
zbaof7223732012-04-13 13:42:15 +0800[diff] [blame]71config HIGH_SCRATCH_MEMORY_SIZE
72 hex
73 # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
74 default 0x71000
75 depends on CPU_AMD_AGESA_FAMILY14