Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpigen.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 7 | #include <device/i2c_bus.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 8 | #include <device/i2c_simple.h> |
Duncan Laurie | 222381e | 2016-06-21 10:41:19 -0700 | [diff] [blame] | 9 | #include <string.h> |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 10 | #include <timer.h> |
Felix Held | a704156 | 2022-01-31 14:21:57 +0100 | [diff] [blame] | 11 | #include <types.h> |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 12 | #include "dw_i2c.h" |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 13 | |
Duncan Laurie | a87170b | 2016-11-03 10:43:14 -0700 | [diff] [blame] | 14 | /* Use a ~10ms timeout for various operations */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 15 | #define DW_I2C_TIMEOUT_US 10000 |
Jes Klinke | 19baa9d | 2022-02-22 16:00:09 -0800 | [diff] [blame] | 16 | /* Timeout for waiting for FIFO to flush */ |
| 17 | #define DW_I2C_FLUSH_TIMEOUT_US 160000 |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 18 | |
| 19 | /* High and low times in different speed modes (in ns) */ |
| 20 | enum { |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 21 | /* SDA Hold Time */ |
| 22 | DEFAULT_SDA_HOLD_TIME = 300, |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 23 | /* Standard Speed */ |
| 24 | MIN_SS_SCL_HIGHTIME = 4000, |
| 25 | MIN_SS_SCL_LOWTIME = 4700, |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 26 | /* Fast Speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 27 | MIN_FS_SCL_HIGHTIME = 600, |
| 28 | MIN_FS_SCL_LOWTIME = 1300, |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 29 | /* Fast Plus Speed */ |
| 30 | MIN_FP_SCL_HIGHTIME = 260, |
| 31 | MIN_FP_SCL_LOWTIME = 500, |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 32 | /* High Speed */ |
| 33 | MIN_HS_SCL_HIGHTIME = 60, |
| 34 | MIN_HS_SCL_LOWTIME = 160, |
| 35 | }; |
| 36 | |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 37 | /* Frequency represented as ticks per ns. Can also be used to calculate |
| 38 | * the number of ticks to meet a time target or the period. */ |
| 39 | struct freq { |
| 40 | uint32_t ticks; |
| 41 | uint32_t ns; |
| 42 | }; |
| 43 | |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 44 | /* Control register definitions */ |
| 45 | enum { |
| 46 | CONTROL_MASTER_MODE = (1 << 0), |
| 47 | CONTROL_SPEED_SS = (1 << 1), |
Felix Held | 6151ff3 | 2022-02-03 15:31:55 +0100 | [diff] [blame] | 48 | CONTROL_SPEED_FS = (2 << 1), |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 49 | CONTROL_SPEED_HS = (3 << 1), |
| 50 | CONTROL_SPEED_MASK = (3 << 1), |
| 51 | CONTROL_10BIT_SLAVE = (1 << 3), |
| 52 | CONTROL_10BIT_MASTER = (1 << 4), |
| 53 | CONTROL_RESTART_ENABLE = (1 << 5), |
| 54 | CONTROL_SLAVE_DISABLE = (1 << 6), |
| 55 | }; |
| 56 | |
| 57 | /* Command/Data register definitions */ |
| 58 | enum { |
| 59 | CMD_DATA_CMD = (1 << 8), |
| 60 | CMD_DATA_STOP = (1 << 9), |
| 61 | }; |
| 62 | |
| 63 | /* Status register definitions */ |
| 64 | enum { |
| 65 | STATUS_ACTIVITY = (1 << 0), |
| 66 | STATUS_TX_FIFO_NOT_FULL = (1 << 1), |
| 67 | STATUS_TX_FIFO_EMPTY = (1 << 2), |
| 68 | STATUS_RX_FIFO_NOT_EMPTY = (1 << 3), |
| 69 | STATUS_RX_FIFO_FULL = (1 << 4), |
| 70 | STATUS_MASTER_ACTIVITY = (1 << 5), |
| 71 | STATUS_SLAVE_ACTIVITY = (1 << 6), |
| 72 | }; |
| 73 | |
| 74 | /* Enable register definitions */ |
| 75 | enum { |
| 76 | ENABLE_CONTROLLER = (1 << 0), |
| 77 | }; |
| 78 | |
| 79 | /* Interrupt status register definitions */ |
| 80 | enum { |
| 81 | INTR_STAT_RX_UNDER = (1 << 0), |
| 82 | INTR_STAT_RX_OVER = (1 << 1), |
| 83 | INTR_STAT_RX_FULL = (1 << 2), |
| 84 | INTR_STAT_TX_OVER = (1 << 3), |
| 85 | INTR_STAT_TX_EMPTY = (1 << 4), |
| 86 | INTR_STAT_RD_REQ = (1 << 5), |
| 87 | INTR_STAT_TX_ABORT = (1 << 6), |
| 88 | INTR_STAT_RX_DONE = (1 << 7), |
| 89 | INTR_STAT_ACTIVITY = (1 << 8), |
| 90 | INTR_STAT_STOP_DET = (1 << 9), |
| 91 | INTR_STAT_START_DET = (1 << 10), |
| 92 | INTR_STAT_GEN_CALL = (1 << 11), |
| 93 | }; |
| 94 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 95 | /* I2C Controller MMIO register space */ |
| 96 | struct dw_i2c_regs { |
Raul E Rangel | 6191b85 | 2020-04-09 11:37:05 -0600 | [diff] [blame] | 97 | uint32_t control; /* 0x0 */ |
| 98 | uint32_t target_addr; /* 0x4 */ |
| 99 | uint32_t slave_addr; /* 0x8 */ |
| 100 | uint32_t master_addr; /* 0xc */ |
| 101 | uint32_t cmd_data; /* 0x10 */ |
| 102 | uint32_t ss_scl_hcnt; /* 0x14 */ |
| 103 | uint32_t ss_scl_lcnt; /* 0x18 */ |
| 104 | uint32_t fs_scl_hcnt; /* 0x1c */ |
| 105 | uint32_t fs_scl_lcnt; /* 0x20 */ |
| 106 | uint32_t hs_scl_hcnt; /* 0x24 */ |
| 107 | uint32_t hs_scl_lcnt; /* 0x28 */ |
| 108 | uint32_t intr_stat; /* 0x2c */ |
| 109 | uint32_t intr_mask; /* 0x30 */ |
| 110 | uint32_t raw_intr_stat; /* 0x34 */ |
| 111 | uint32_t rx_thresh; /* 0x38 */ |
| 112 | uint32_t tx_thresh; /* 0x3c */ |
| 113 | uint32_t clear_intr; /* 0x40 */ |
| 114 | uint32_t clear_rx_under_intr; /* 0x44 */ |
| 115 | uint32_t clear_rx_over_intr; /* 0x48 */ |
| 116 | uint32_t clear_tx_over_intr; /* 0x4c */ |
| 117 | uint32_t clear_rd_req_intr; /* 0x50 */ |
| 118 | uint32_t clear_tx_abrt_intr; /* 0x54 */ |
| 119 | uint32_t clear_rx_done_intr; /* 0x58 */ |
| 120 | uint32_t clear_activity_intr; /* 0x5c */ |
| 121 | uint32_t clear_stop_det_intr; /* 0x60 */ |
| 122 | uint32_t clear_start_det_intr; /* 0x64 */ |
| 123 | uint32_t clear_gen_call_intr; /* 0x68 */ |
| 124 | uint32_t enable; /* 0x6c */ |
| 125 | uint32_t status; /* 0x70 */ |
| 126 | uint32_t tx_level; /* 0x74 */ |
| 127 | uint32_t rx_level; /* 0x78 */ |
| 128 | uint32_t sda_hold; /* 0x7c */ |
| 129 | uint32_t tx_abort_source; /* 0x80 */ |
| 130 | uint32_t slv_data_nak_only; /* 0x84 */ |
| 131 | uint32_t dma_cr; /* 0x88 */ |
| 132 | uint32_t dma_tdlr; /* 0x8c */ |
| 133 | uint32_t dma_rdlr; /* 0x90 */ |
| 134 | uint32_t sda_setup; /* 0x94 */ |
| 135 | uint32_t ack_general_call; /* 0x98 */ |
| 136 | uint32_t enable_status; /* 0x9c */ |
| 137 | uint32_t fs_spklen; /* 0xa0 */ |
| 138 | uint32_t hs_spklen; /* 0xa4 */ |
| 139 | uint32_t clr_restart_det; /* 0xa8 */ |
| 140 | uint32_t reserved[18]; /* 0xac - 0xf0 */ |
| 141 | uint32_t comp_param1; /* 0xf4 */ |
| 142 | uint32_t comp_version; /* 0xf8 */ |
| 143 | uint32_t comp_type; /* 0xfc */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 144 | } __packed; |
| 145 | |
Raul E Rangel | 6191b85 | 2020-04-09 11:37:05 -0600 | [diff] [blame] | 146 | /* Constant value defined in the DesignWare DW_apb_i2c Databook. */ |
| 147 | #define DW_I2C_COMP_TYPE 0x44570140 |
| 148 | |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 149 | static const struct i2c_descriptor { |
| 150 | enum i2c_speed speed; |
| 151 | struct freq freq; |
| 152 | int min_thigh_ns; |
| 153 | int min_tlow_ns; |
| 154 | } speed_descriptors[] = { |
| 155 | { |
| 156 | .speed = I2C_SPEED_STANDARD, |
| 157 | .freq = { |
| 158 | .ticks = 100, |
| 159 | .ns = 1000*1000, |
| 160 | }, |
| 161 | .min_thigh_ns = MIN_SS_SCL_HIGHTIME, |
| 162 | .min_tlow_ns = MIN_SS_SCL_LOWTIME, |
| 163 | }, |
| 164 | { |
| 165 | .speed = I2C_SPEED_FAST, |
| 166 | .freq = { |
| 167 | .ticks = 400, |
| 168 | .ns = 1000*1000, |
| 169 | }, |
| 170 | .min_thigh_ns = MIN_FS_SCL_HIGHTIME, |
| 171 | .min_tlow_ns = MIN_FS_SCL_LOWTIME, |
| 172 | }, |
| 173 | { |
| 174 | .speed = I2C_SPEED_FAST_PLUS, |
| 175 | .freq = { |
| 176 | .ticks = 1, |
| 177 | .ns = 1000, |
| 178 | }, |
| 179 | .min_thigh_ns = MIN_FP_SCL_HIGHTIME, |
| 180 | .min_tlow_ns = MIN_FP_SCL_LOWTIME, |
| 181 | }, |
| 182 | { |
| 183 | /* 100pF max capacitance */ |
| 184 | .speed = I2C_SPEED_HIGH, |
| 185 | .freq = { |
| 186 | .ticks = 3400, |
| 187 | .ns = 1000*1000, |
| 188 | }, |
| 189 | .min_thigh_ns = MIN_HS_SCL_HIGHTIME, |
| 190 | .min_tlow_ns = MIN_HS_SCL_LOWTIME, |
| 191 | }, |
| 192 | }; |
| 193 | |
| 194 | static const struct soc_clock { |
| 195 | int clk_speed_mhz; |
| 196 | struct freq freq; |
| 197 | } soc_clocks[] = { |
| 198 | { |
| 199 | .clk_speed_mhz = 120, |
| 200 | .freq = { |
| 201 | .ticks = 120, |
| 202 | .ns = 1000, |
| 203 | }, |
| 204 | }, |
| 205 | { |
| 206 | .clk_speed_mhz = 133, |
| 207 | .freq = { |
| 208 | .ticks = 400, |
| 209 | .ns = 3000, |
| 210 | }, |
| 211 | }, |
Duncan Laurie | 4afefd6 | 2018-12-05 15:38:13 -0800 | [diff] [blame] | 212 | { |
Martin Roth | ba37b94 | 2019-12-16 23:19:29 -0700 | [diff] [blame] | 213 | .clk_speed_mhz = 150, |
| 214 | .freq = { |
| 215 | .ticks = 600, |
| 216 | .ns = 4000, |
| 217 | }, |
| 218 | }, |
| 219 | { |
Duncan Laurie | 4afefd6 | 2018-12-05 15:38:13 -0800 | [diff] [blame] | 220 | .clk_speed_mhz = 216, |
| 221 | .freq = { |
| 222 | .ticks = 1080, |
| 223 | .ns = 5000, |
| 224 | }, |
| 225 | }, |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 226 | }; |
| 227 | |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 228 | static const struct i2c_descriptor *get_bus_descriptor(enum i2c_speed speed) |
| 229 | { |
| 230 | size_t i; |
| 231 | |
| 232 | for (i = 0; i < ARRAY_SIZE(speed_descriptors); i++) |
| 233 | if (speed == speed_descriptors[i].speed) |
| 234 | return &speed_descriptors[i]; |
| 235 | |
| 236 | return NULL; |
| 237 | } |
| 238 | |
| 239 | static const struct soc_clock *get_soc_descriptor(int ic_clk) |
| 240 | { |
| 241 | size_t i; |
| 242 | |
| 243 | for (i = 0; i < ARRAY_SIZE(soc_clocks); i++) |
| 244 | if (ic_clk == soc_clocks[i].clk_speed_mhz) |
| 245 | return &soc_clocks[i]; |
| 246 | |
| 247 | return NULL; |
| 248 | } |
| 249 | |
| 250 | static int counts_from_time(const struct freq *f, int ns) |
| 251 | { |
| 252 | return DIV_ROUND_UP(f->ticks * ns, f->ns); |
| 253 | } |
| 254 | |
| 255 | static int counts_from_freq(const struct freq *fast, const struct freq *slow) |
| 256 | { |
| 257 | return DIV_ROUND_UP(fast->ticks * slow->ns, fast->ns * slow->ticks); |
| 258 | } |
| 259 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 260 | /* Enable this I2C controller */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 261 | static void dw_i2c_enable(struct dw_i2c_regs *regs) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 262 | { |
| 263 | uint32_t enable = read32(®s->enable); |
| 264 | |
| 265 | if (!(enable & ENABLE_CONTROLLER)) |
| 266 | write32(®s->enable, enable | ENABLE_CONTROLLER); |
| 267 | } |
| 268 | |
| 269 | /* Disable this I2C controller */ |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 270 | static enum cb_err dw_i2c_disable(struct dw_i2c_regs *regs) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 271 | { |
| 272 | uint32_t enable = read32(®s->enable); |
| 273 | |
| 274 | if (enable & ENABLE_CONTROLLER) { |
| 275 | struct stopwatch sw; |
| 276 | |
| 277 | write32(®s->enable, enable & ~ENABLE_CONTROLLER); |
| 278 | |
| 279 | /* Wait for enable bit to clear */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 280 | stopwatch_init_usecs_expire(&sw, DW_I2C_TIMEOUT_US); |
Duncan Laurie | 772555a2 | 2016-09-12 11:20:27 -0700 | [diff] [blame] | 281 | while (read32(®s->enable_status) & ENABLE_CONTROLLER) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 282 | if (stopwatch_expired(&sw)) |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 283 | return CB_ERR; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 284 | } |
| 285 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 286 | return CB_SUCCESS; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | /* Wait for this I2C controller to go idle for transmit */ |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 290 | static enum cb_err dw_i2c_wait_for_bus_idle(struct dw_i2c_regs *regs) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 291 | { |
| 292 | struct stopwatch sw; |
| 293 | |
| 294 | /* Start timeout for up to 16 bytes in FIFO */ |
Jes Klinke | 19baa9d | 2022-02-22 16:00:09 -0800 | [diff] [blame] | 295 | stopwatch_init_usecs_expire(&sw, DW_I2C_FLUSH_TIMEOUT_US); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 296 | |
| 297 | while (!stopwatch_expired(&sw)) { |
| 298 | uint32_t status = read32(®s->status); |
| 299 | |
| 300 | /* Check for master activity and keep waiting */ |
| 301 | if (status & STATUS_MASTER_ACTIVITY) |
| 302 | continue; |
| 303 | |
| 304 | /* Check for TX FIFO empty to indicate TX idle */ |
| 305 | if (status & STATUS_TX_FIFO_EMPTY) |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 306 | return CB_SUCCESS; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 307 | } |
| 308 | |
| 309 | /* Timed out while waiting for bus to go idle */ |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 310 | return CB_ERR; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 311 | } |
| 312 | |
| 313 | /* Transfer one byte of one segment, sending stop bit if requested */ |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 314 | static enum cb_err dw_i2c_transfer_byte(struct dw_i2c_regs *regs, |
| 315 | const struct i2c_msg *segment, |
| 316 | size_t byte, int send_stop) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 317 | { |
| 318 | struct stopwatch sw; |
| 319 | uint32_t cmd = CMD_DATA_CMD; /* Read op */ |
| 320 | |
Jes Klinke | 19baa9d | 2022-02-22 16:00:09 -0800 | [diff] [blame] | 321 | stopwatch_init_usecs_expire(&sw, CONFIG_I2C_TRANSFER_TIMEOUT_US); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 322 | |
Nico Huber | 029dfff | 2017-07-12 17:59:16 +0200 | [diff] [blame] | 323 | if (!(segment->flags & I2C_M_RD)) { |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 324 | /* Write op only: Wait for FIFO not full */ |
| 325 | while (!(read32(®s->status) & STATUS_TX_FIFO_NOT_FULL)) { |
| 326 | if (stopwatch_expired(&sw)) { |
| 327 | printk(BIOS_ERR, "I2C transmit timeout\n"); |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 328 | return CB_ERR; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 329 | } |
| 330 | } |
| 331 | cmd = segment->buf[byte]; |
| 332 | } |
| 333 | |
| 334 | /* Send stop on last byte, if desired */ |
| 335 | if (send_stop && byte == segment->len - 1) |
| 336 | cmd |= CMD_DATA_STOP; |
| 337 | |
| 338 | write32(®s->cmd_data, cmd); |
| 339 | |
Nico Huber | 029dfff | 2017-07-12 17:59:16 +0200 | [diff] [blame] | 340 | if (segment->flags & I2C_M_RD) { |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 341 | /* Read op only: Wait for FIFO data and store it */ |
| 342 | while (!(read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY)) { |
| 343 | if (stopwatch_expired(&sw)) { |
| 344 | printk(BIOS_ERR, "I2C receive timeout\n"); |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 345 | return CB_ERR; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 346 | } |
| 347 | } |
| 348 | segment->buf[byte] = read32(®s->cmd_data); |
| 349 | } |
| 350 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 351 | return CB_SUCCESS; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 352 | } |
| 353 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 354 | static enum cb_err _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments, |
| 355 | size_t count) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 356 | { |
| 357 | struct stopwatch sw; |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 358 | struct dw_i2c_regs *regs; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 359 | size_t byte; |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 360 | enum cb_err ret = CB_ERR; |
Matt DeVillier | 5709713 | 2022-04-11 17:10:09 -0500 | [diff] [blame^] | 361 | bool seg_zero_len = segments->len == 0; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 362 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 363 | regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 364 | if (!regs) { |
| 365 | printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 366 | return CB_ERR; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 367 | } |
| 368 | |
Aaron Durbin | 97d58bc | 2018-01-30 17:29:08 -0700 | [diff] [blame] | 369 | /* The assumption is that the host controller is disabled -- either |
Elyes HAOUAS | 1895838 | 2018-08-07 12:23:16 +0200 | [diff] [blame] | 370 | after running this function or from performing the initialization |
Aaron Durbin | 97d58bc | 2018-01-30 17:29:08 -0700 | [diff] [blame] | 371 | sequence in dw_i2c_init(). */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 372 | |
Aaron Durbin | 97d58bc | 2018-01-30 17:29:08 -0700 | [diff] [blame] | 373 | /* Set target slave address */ |
| 374 | write32(®s->target_addr, segments->slave); |
| 375 | |
| 376 | dw_i2c_enable(regs); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 377 | |
Matt DeVillier | 5709713 | 2022-04-11 17:10:09 -0500 | [diff] [blame^] | 378 | if (seg_zero_len) |
| 379 | /* stop immediately */ |
| 380 | write32(®s->cmd_data, CMD_DATA_STOP); |
| 381 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 382 | /* Process each segment */ |
| 383 | while (count--) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 384 | if (CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)) { |
Duncan Laurie | f8a7b2c | 2016-09-12 11:21:40 -0700 | [diff] [blame] | 385 | printk(BIOS_DEBUG, "i2c %u:%02x %s %d bytes : ", |
Nico Huber | 029dfff | 2017-07-12 17:59:16 +0200 | [diff] [blame] | 386 | bus, segments->slave, |
| 387 | (segments->flags & I2C_M_RD) ? "R" : "W", |
Duncan Laurie | f8a7b2c | 2016-09-12 11:21:40 -0700 | [diff] [blame] | 388 | segments->len); |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 389 | } |
Duncan Laurie | f8a7b2c | 2016-09-12 11:21:40 -0700 | [diff] [blame] | 390 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 391 | /* Read or write each byte in segment */ |
| 392 | for (byte = 0; byte < segments->len; byte++) { |
| 393 | /* |
| 394 | * Set stop condition on final segment only. |
| 395 | * Repeated start will be automatically generated |
| 396 | * by the controller on R->W or W->R switch. |
| 397 | */ |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 398 | if (dw_i2c_transfer_byte(regs, segments, byte, count == 0) != |
| 399 | CB_SUCCESS) { |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 400 | printk(BIOS_ERR, "I2C %s failed: bus %u " |
Nico Huber | 029dfff | 2017-07-12 17:59:16 +0200 | [diff] [blame] | 401 | "addr 0x%02x\n", |
| 402 | (segments->flags & I2C_M_RD) ? |
| 403 | "read" : "write", bus, segments->slave); |
Duncan Laurie | 772555a2 | 2016-09-12 11:20:27 -0700 | [diff] [blame] | 404 | goto out; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 405 | } |
| 406 | } |
Duncan Laurie | f8a7b2c | 2016-09-12 11:21:40 -0700 | [diff] [blame] | 407 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 408 | if (CONFIG(DRIVERS_I2C_DESIGNWARE_DEBUG)) { |
Duncan Laurie | f8a7b2c | 2016-09-12 11:21:40 -0700 | [diff] [blame] | 409 | int j; |
| 410 | for (j = 0; j < segments->len; j++) |
| 411 | printk(BIOS_DEBUG, "%02x ", segments->buf[j]); |
Maulik V Vaghela | 794d097 | 2018-03-20 16:52:00 +0530 | [diff] [blame] | 412 | printk(BIOS_DEBUG, "\n"); |
Duncan Laurie | f8a7b2c | 2016-09-12 11:21:40 -0700 | [diff] [blame] | 413 | } |
| 414 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 415 | segments++; |
| 416 | } |
| 417 | |
| 418 | /* Wait for interrupt status to indicate transfer is complete */ |
Jes Klinke | 19baa9d | 2022-02-22 16:00:09 -0800 | [diff] [blame] | 419 | stopwatch_init_usecs_expire(&sw, CONFIG_I2C_TRANSFER_TIMEOUT_US); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 420 | while (!(read32(®s->raw_intr_stat) & INTR_STAT_STOP_DET)) { |
| 421 | if (stopwatch_expired(&sw)) { |
| 422 | printk(BIOS_ERR, "I2C stop bit not received\n"); |
Duncan Laurie | 772555a2 | 2016-09-12 11:20:27 -0700 | [diff] [blame] | 423 | goto out; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 424 | } |
| 425 | } |
| 426 | |
| 427 | /* Read to clear INTR_STAT_STOP_DET */ |
| 428 | read32(®s->clear_stop_det_intr); |
| 429 | |
Kangheui Won | b2c39b5 | 2020-11-09 17:49:48 +1100 | [diff] [blame] | 430 | /* Check TX abort */ |
| 431 | if (read32(®s->raw_intr_stat) & INTR_STAT_TX_ABORT) { |
Matt DeVillier | 5709713 | 2022-04-11 17:10:09 -0500 | [diff] [blame^] | 432 | printk(seg_zero_len ? BIOS_SPEW : BIOS_ERR, "I2C TX abort detected (%08x)\n", |
| 433 | read32(®s->tx_abort_source)); |
Kangheui Won | b2c39b5 | 2020-11-09 17:49:48 +1100 | [diff] [blame] | 434 | /* clear INTR_STAT_TX_ABORT */ |
| 435 | read32(®s->clear_tx_abrt_intr); |
| 436 | goto out; |
| 437 | } |
| 438 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 439 | /* Wait for the bus to go idle */ |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 440 | if (dw_i2c_wait_for_bus_idle(regs) != CB_SUCCESS) { |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 441 | printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); |
Duncan Laurie | 772555a2 | 2016-09-12 11:20:27 -0700 | [diff] [blame] | 442 | goto out; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 443 | } |
| 444 | |
| 445 | /* Flush the RX FIFO in case it is not empty */ |
Jes Klinke | 19baa9d | 2022-02-22 16:00:09 -0800 | [diff] [blame] | 446 | stopwatch_init_usecs_expire(&sw, DW_I2C_FLUSH_TIMEOUT_US); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 447 | while (read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY) { |
| 448 | if (stopwatch_expired(&sw)) { |
| 449 | printk(BIOS_ERR, "I2C timeout flushing RX FIFO\n"); |
Duncan Laurie | 772555a2 | 2016-09-12 11:20:27 -0700 | [diff] [blame] | 450 | goto out; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 451 | } |
| 452 | read32(®s->cmd_data); |
| 453 | } |
| 454 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 455 | ret = CB_SUCCESS; |
Duncan Laurie | 772555a2 | 2016-09-12 11:20:27 -0700 | [diff] [blame] | 456 | |
| 457 | out: |
| 458 | read32(®s->clear_intr); |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 459 | dw_i2c_disable(regs); |
Duncan Laurie | 772555a2 | 2016-09-12 11:20:27 -0700 | [diff] [blame] | 460 | return ret; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 461 | } |
| 462 | |
Felix Held | abdf684 | 2022-01-31 16:02:05 +0100 | [diff] [blame] | 463 | static enum cb_err dw_i2c_transfer(unsigned int bus, const struct i2c_msg *msg, size_t count) |
Aaron Durbin | 97d58bc | 2018-01-30 17:29:08 -0700 | [diff] [blame] | 464 | { |
| 465 | const struct i2c_msg *orig_msg = msg; |
| 466 | size_t i; |
| 467 | size_t start; |
| 468 | uint16_t addr; |
| 469 | |
Matt DeVillier | 5709713 | 2022-04-11 17:10:09 -0500 | [diff] [blame^] | 470 | if (!msg) |
Aaron Durbin | 97d58bc | 2018-01-30 17:29:08 -0700 | [diff] [blame] | 471 | return -1; |
| 472 | |
| 473 | /* Break up the transfers at the differing slave address boundary. */ |
| 474 | addr = orig_msg->slave; |
| 475 | |
| 476 | for (i = 0, start = 0; i < count; i++, msg++) { |
| 477 | if (addr != msg->slave) { |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 478 | if (_dw_i2c_transfer(bus, &orig_msg[start], i - start) != CB_SUCCESS) |
Felix Held | 8ed02de8 | 2022-01-31 15:59:17 +0100 | [diff] [blame] | 479 | return CB_ERR; |
Aaron Durbin | 97d58bc | 2018-01-30 17:29:08 -0700 | [diff] [blame] | 480 | start = i; |
| 481 | addr = msg->slave; |
| 482 | } |
| 483 | } |
| 484 | |
Felix Held | 8ed02de8 | 2022-01-31 15:59:17 +0100 | [diff] [blame] | 485 | return _dw_i2c_transfer(bus, &orig_msg[start], count - start); |
Aaron Durbin | 97d58bc | 2018-01-30 17:29:08 -0700 | [diff] [blame] | 486 | } |
| 487 | |
Nico Huber | 5817386 | 2017-08-01 17:09:35 +0200 | [diff] [blame] | 488 | /* Global I2C bus handler, defined in include/device/i2c_simple.h */ |
| 489 | int platform_i2c_transfer(unsigned int bus, struct i2c_msg *msg, int count) |
| 490 | { |
Felix Held | 8ed02de8 | 2022-01-31 15:59:17 +0100 | [diff] [blame] | 491 | return dw_i2c_transfer(bus, msg, count < 0 ? 0 : count) == CB_SUCCESS ? 0 : -1; |
Nico Huber | 5817386 | 2017-08-01 17:09:35 +0200 | [diff] [blame] | 492 | } |
| 493 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 494 | static enum cb_err dw_i2c_set_speed_config(unsigned int bus, |
| 495 | const struct dw_i2c_speed_config *config) |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 496 | { |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 497 | struct dw_i2c_regs *regs; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 498 | void *hcnt_reg, *lcnt_reg; |
| 499 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 500 | regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 501 | if (!regs || !config) |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 502 | return CB_ERR; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 503 | |
| 504 | /* Nothing to do if no values are set */ |
| 505 | if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold) |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 506 | return CB_SUCCESS; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 507 | |
Naresh G Solanki | 14deaee | 2017-07-19 17:14:33 +0530 | [diff] [blame] | 508 | if (config->speed >= I2C_SPEED_HIGH) { |
| 509 | /* High and Fast Ultra speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 510 | hcnt_reg = ®s->hs_scl_hcnt; |
| 511 | lcnt_reg = ®s->hs_scl_lcnt; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 512 | } else if (config->speed >= I2C_SPEED_FAST) { |
Naresh G Solanki | 14deaee | 2017-07-19 17:14:33 +0530 | [diff] [blame] | 513 | /* Fast and Fast-Plus speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 514 | hcnt_reg = ®s->fs_scl_hcnt; |
| 515 | lcnt_reg = ®s->fs_scl_lcnt; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 516 | } else { |
| 517 | /* Standard speed */ |
| 518 | hcnt_reg = ®s->ss_scl_hcnt; |
| 519 | lcnt_reg = ®s->ss_scl_lcnt; |
| 520 | } |
| 521 | |
| 522 | /* SCL count must be set after the speed is selected */ |
| 523 | if (config->scl_hcnt) |
| 524 | write32(hcnt_reg, config->scl_hcnt); |
| 525 | if (config->scl_lcnt) |
| 526 | write32(lcnt_reg, config->scl_lcnt); |
| 527 | |
| 528 | /* Set SDA Hold Time register */ |
| 529 | if (config->sda_hold) |
| 530 | write32(®s->sda_hold, config->sda_hold); |
| 531 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 532 | return CB_SUCCESS; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 533 | } |
| 534 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 535 | static enum cb_err dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs, |
| 536 | enum i2c_speed speed, |
| 537 | const struct dw_i2c_bus_config *bcfg, |
| 538 | int ic_clk, |
| 539 | struct dw_i2c_speed_config *config) |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 540 | { |
| 541 | const struct i2c_descriptor *bus; |
| 542 | const struct soc_clock *soc; |
| 543 | int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt, spk_cnt; |
| 544 | int hcnt, lcnt, period_cnt, diff, tot; |
Aaron Durbin | c5f10f9 | 2017-03-31 14:46:26 -0500 | [diff] [blame] | 545 | int data_hold_time_ns; |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 546 | |
| 547 | bus = get_bus_descriptor(speed); |
| 548 | soc = get_soc_descriptor(ic_clk); |
| 549 | |
| 550 | if (bus == NULL) { |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 551 | printk(BIOS_ERR, "dw_i2c: invalid bus speed %d\n", speed); |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 552 | return CB_ERR; |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | if (soc == NULL) { |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 556 | printk(BIOS_ERR, "dw_i2c: invalid SoC clock speed %d MHz\n", |
Aaron Durbin | bff8c5ec | 2016-11-18 08:10:35 -0600 | [diff] [blame] | 557 | ic_clk); |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 558 | return CB_ERR; |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | /* Get the proper spike suppression count based on target speed. */ |
| 562 | if (speed >= I2C_SPEED_HIGH) |
| 563 | spk_cnt = read32(®s->hs_spklen); |
| 564 | else |
| 565 | spk_cnt = read32(®s->fs_spklen); |
| 566 | |
| 567 | /* Find the period, rise, fall, min tlow, and min thigh in terms of |
| 568 | * counts of SoC clock. */ |
| 569 | period_cnt = counts_from_freq(&soc->freq, &bus->freq); |
| 570 | rise_cnt = counts_from_time(&soc->freq, bcfg->rise_time_ns); |
| 571 | fall_cnt = counts_from_time(&soc->freq, bcfg->fall_time_ns); |
| 572 | min_tlow_cnt = counts_from_time(&soc->freq, bus->min_tlow_ns); |
| 573 | min_thigh_cnt = counts_from_time(&soc->freq, bus->min_thigh_ns); |
| 574 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 575 | printk(DW_I2C_DEBUG, "dw_i2c: SoC %d/%d ns Bus: %d/%d ns\n", |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 576 | soc->freq.ticks, soc->freq.ns, bus->freq.ticks, bus->freq.ns); |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 577 | printk(DW_I2C_DEBUG, |
Reka Norman | 4bc2ca5 | 2022-04-12 09:11:35 +1000 | [diff] [blame] | 578 | "dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n", |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 579 | period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt, |
| 580 | spk_cnt); |
| 581 | |
| 582 | /* |
| 583 | * Back solve for hcnt and lcnt according to the following equations. |
| 584 | * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time |
| 585 | * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time |
| 586 | */ |
| 587 | hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt; |
| 588 | lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1; |
| 589 | |
| 590 | if (hcnt < 0 || lcnt < 0) { |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 591 | printk(BIOS_ERR, "dw_i2c: bad counts. hcnt = %d lcnt = %d\n", |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 592 | hcnt, lcnt); |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 593 | return CB_ERR; |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 594 | } |
| 595 | |
| 596 | /* Now add things back up to ensure the period is hit. If off, |
| 597 | * split the difference and bias to lcnt for remainder. */ |
| 598 | tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1; |
| 599 | |
| 600 | if (tot < period_cnt) { |
| 601 | diff = (period_cnt - tot) / 2; |
| 602 | hcnt += diff; |
| 603 | lcnt += diff; |
| 604 | tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1; |
| 605 | lcnt += period_cnt - tot; |
| 606 | } |
| 607 | |
| 608 | config->speed = speed; |
| 609 | config->scl_lcnt = lcnt; |
| 610 | config->scl_hcnt = hcnt; |
Aaron Durbin | c5f10f9 | 2017-03-31 14:46:26 -0500 | [diff] [blame] | 611 | |
| 612 | /* Use internal default unless other value is specified. */ |
| 613 | data_hold_time_ns = DEFAULT_SDA_HOLD_TIME; |
| 614 | if (bcfg->data_hold_time_ns) |
| 615 | data_hold_time_ns = bcfg->data_hold_time_ns; |
| 616 | |
| 617 | config->sda_hold = counts_from_time(&soc->freq, data_hold_time_ns); |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 618 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 619 | printk(DW_I2C_DEBUG, "dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 620 | hcnt, lcnt, config->sda_hold); |
| 621 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 622 | return CB_SUCCESS; |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 623 | } |
| 624 | |
Felix Held | 7edf910 | 2022-01-31 15:56:14 +0100 | [diff] [blame] | 625 | enum cb_err dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr, |
Aaron Durbin | 2b3e0cd | 2016-11-09 23:20:30 -0600 | [diff] [blame] | 626 | enum i2c_speed speed, |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 627 | const struct dw_i2c_bus_config *bcfg, |
| 628 | struct dw_i2c_speed_config *config) |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 629 | { |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 630 | const int ic_clk = CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ; |
| 631 | struct dw_i2c_regs *regs; |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 632 | int i; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 633 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 634 | regs = (struct dw_i2c_regs *)dw_i2c_addr; |
| 635 | |
| 636 | _Static_assert(CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ != 0, |
| 637 | "DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ can't be zero!"); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 638 | |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 639 | /* Apply board specific override for this speed if found */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 640 | for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) { |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 641 | if (bcfg->speed_config[i].speed != speed) |
| 642 | continue; |
| 643 | memcpy(config, &bcfg->speed_config[i], sizeof(*config)); |
Felix Held | 7edf910 | 2022-01-31 15:56:14 +0100 | [diff] [blame] | 644 | return CB_SUCCESS; |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 645 | } |
| 646 | |
Kyösti Mälkki | 2263e9b | 2021-04-28 09:13:21 +0300 | [diff] [blame] | 647 | /* Use the time calculation. */ |
Felix Held | 7edf910 | 2022-01-31 15:56:14 +0100 | [diff] [blame] | 648 | return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg, ic_clk, config); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 649 | } |
| 650 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 651 | static enum cb_err dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed, |
| 652 | const struct dw_i2c_bus_config *bcfg) |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 653 | { |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 654 | struct dw_i2c_regs *regs; |
| 655 | struct dw_i2c_speed_config config; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 656 | uint32_t control; |
| 657 | |
| 658 | /* Clock must be provided by Kconfig */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 659 | regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 660 | if (!regs || !speed) |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 661 | return CB_ERR; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 662 | |
| 663 | control = read32(®s->control); |
| 664 | control &= ~CONTROL_SPEED_MASK; |
| 665 | |
Naresh G Solanki | 14deaee | 2017-07-19 17:14:33 +0530 | [diff] [blame] | 666 | if (speed >= I2C_SPEED_HIGH) { |
| 667 | /* High and Fast-Ultra speed share config registers */ |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 668 | control |= CONTROL_SPEED_HS; |
| 669 | } else if (speed >= I2C_SPEED_FAST) { |
Naresh G Solanki | 14deaee | 2017-07-19 17:14:33 +0530 | [diff] [blame] | 670 | /* Fast speed and Fast-Plus */ |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 671 | control |= CONTROL_SPEED_FS; |
| 672 | } else { |
| 673 | /* Standard speed */ |
| 674 | control |= CONTROL_SPEED_SS; |
| 675 | } |
| 676 | |
| 677 | /* Generate speed config based on clock */ |
Felix Held | 7edf910 | 2022-01-31 15:56:14 +0100 | [diff] [blame] | 678 | if (dw_i2c_gen_speed_config((uintptr_t)regs, speed, bcfg, &config) != CB_SUCCESS) |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 679 | return CB_ERR; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 680 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 681 | /* Select this speed in the control register */ |
| 682 | write32(®s->control, control); |
| 683 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 684 | /* Write the speed config that was generated earlier */ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 685 | dw_i2c_set_speed_config(bus, &config); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 686 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 687 | return CB_SUCCESS; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 688 | } |
| 689 | |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 690 | /* |
| 691 | * Initialize this bus controller and set the speed. |
| 692 | * |
| 693 | * The bus speed can be passed in Hz or using values from device/i2c.h and |
| 694 | * will default to I2C_SPEED_FAST if it is not provided. |
| 695 | */ |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 696 | enum cb_err dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 697 | { |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 698 | struct dw_i2c_regs *regs; |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 699 | enum i2c_speed speed; |
| 700 | |
| 701 | if (!bcfg) |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 702 | return CB_ERR; |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 703 | |
| 704 | speed = bcfg->speed ? : I2C_SPEED_FAST; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 705 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 706 | regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 707 | if (!regs) { |
| 708 | printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 709 | return CB_ERR; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 710 | } |
| 711 | |
Raul E Rangel | 6191b85 | 2020-04-09 11:37:05 -0600 | [diff] [blame] | 712 | if (read32(®s->comp_type) != DW_I2C_COMP_TYPE) { |
| 713 | printk(BIOS_ERR, "I2C bus %u has unknown type 0x%x.\n", bus, |
| 714 | read32(®s->comp_type)); |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 715 | return CB_ERR; |
Raul E Rangel | 6191b85 | 2020-04-09 11:37:05 -0600 | [diff] [blame] | 716 | } |
| 717 | |
| 718 | printk(BIOS_DEBUG, "I2C bus %u version 0x%x\n", bus, read32(®s->comp_version)); |
| 719 | |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 720 | if (dw_i2c_disable(regs) != CB_SUCCESS) { |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 721 | printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus); |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 722 | return CB_ERR; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 723 | } |
| 724 | |
| 725 | /* Put controller in master mode with restart enabled */ |
| 726 | write32(®s->control, CONTROL_MASTER_MODE | CONTROL_SLAVE_DISABLE | |
| 727 | CONTROL_RESTART_ENABLE); |
| 728 | |
| 729 | /* Set bus speed to FAST by default */ |
Felix Held | 2a542da | 2022-01-31 14:36:30 +0100 | [diff] [blame] | 730 | if (dw_i2c_set_speed(bus, speed, bcfg) != CB_SUCCESS) { |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 731 | printk(BIOS_ERR, "I2C failed to set speed for bus %u\n", bus); |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 732 | return CB_ERR; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 733 | } |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 734 | |
| 735 | /* Set RX/TX thresholds to smallest values */ |
| 736 | write32(®s->rx_thresh, 0); |
| 737 | write32(®s->tx_thresh, 0); |
| 738 | |
Kangheui Won | b2c39b5 | 2020-11-09 17:49:48 +1100 | [diff] [blame] | 739 | /* Enable stop detection and TX abort interrupt */ |
| 740 | write32(®s->intr_mask, INTR_STAT_STOP_DET | INTR_STAT_TX_ABORT); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 741 | |
Julius Werner | 540a980 | 2019-12-09 13:03:29 -0800 | [diff] [blame] | 742 | printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n", |
Aaron Durbin | 4668ba7 | 2016-11-09 17:09:40 -0600 | [diff] [blame] | 743 | bus, regs, speed / KHz); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 744 | |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 745 | return CB_SUCCESS; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 746 | } |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 747 | |
| 748 | /* |
| 749 | * Write ACPI object to describe speed configuration. |
| 750 | * |
| 751 | * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold } |
| 752 | * |
| 753 | * SSCN: I2C_SPEED_STANDARD |
| 754 | * FMCN: I2C_SPEED_FAST |
| 755 | * FPCN: I2C_SPEED_FAST_PLUS |
| 756 | * HSCN: I2C_SPEED_HIGH |
| 757 | */ |
| 758 | static void dw_i2c_acpi_write_speed_config( |
| 759 | const struct dw_i2c_speed_config *config) |
| 760 | { |
| 761 | if (!config) |
| 762 | return; |
| 763 | if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold) |
| 764 | return; |
| 765 | |
| 766 | if (config->speed >= I2C_SPEED_HIGH) |
| 767 | acpigen_write_name("HSCN"); |
| 768 | else if (config->speed >= I2C_SPEED_FAST_PLUS) |
| 769 | acpigen_write_name("FPCN"); |
| 770 | else if (config->speed >= I2C_SPEED_FAST) |
| 771 | acpigen_write_name("FMCN"); |
| 772 | else |
| 773 | acpigen_write_name("SSCN"); |
| 774 | |
| 775 | /* Package () { scl_lcnt, scl_hcnt, sda_hold } */ |
| 776 | acpigen_write_package(3); |
| 777 | acpigen_write_word(config->scl_hcnt); |
| 778 | acpigen_write_word(config->scl_lcnt); |
| 779 | acpigen_write_dword(config->sda_hold); |
| 780 | acpigen_pop_len(); |
| 781 | } |
| 782 | |
| 783 | /* |
| 784 | * The device should already be enabled and out of reset, |
| 785 | * either from early init in coreboot or SiliconInit in FSP. |
| 786 | */ |
| 787 | void dw_i2c_dev_init(struct device *dev) |
| 788 | { |
| 789 | const struct dw_i2c_bus_config *config; |
| 790 | int bus = dw_i2c_soc_dev_to_bus(dev); |
| 791 | |
| 792 | if (bus < 0) |
| 793 | return; |
| 794 | |
Aaron Durbin | b94a275 | 2018-01-24 16:58:18 -0700 | [diff] [blame] | 795 | config = dw_i2c_get_soc_cfg(bus); |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 796 | |
| 797 | if (!config) |
| 798 | return; |
| 799 | |
| 800 | dw_i2c_init(bus, config); |
| 801 | } |
| 802 | |
| 803 | /* |
| 804 | * Generate I2C timing information into the SSDT for the OS driver to consume, |
| 805 | * optionally applying override values provided by the caller. |
| 806 | */ |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 807 | void dw_i2c_acpi_fill_ssdt(const struct device *dev) |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 808 | { |
| 809 | const struct dw_i2c_bus_config *bcfg; |
| 810 | uintptr_t dw_i2c_addr; |
| 811 | struct dw_i2c_speed_config sgen; |
Tim Wawrzynczak | ba0a393 | 2019-07-17 09:25:59 -0600 | [diff] [blame] | 812 | int bus; |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 813 | const char *path; |
Werner Zeh | 1e02ad3 | 2021-05-31 07:08:17 +0200 | [diff] [blame] | 814 | unsigned int speed, i; |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 815 | |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 816 | bus = dw_i2c_soc_dev_to_bus(dev); |
| 817 | |
| 818 | if (bus < 0) |
| 819 | return; |
| 820 | |
Aaron Durbin | b94a275 | 2018-01-24 16:58:18 -0700 | [diff] [blame] | 821 | bcfg = dw_i2c_get_soc_cfg(bus); |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 822 | |
| 823 | if (!bcfg) |
| 824 | return; |
| 825 | |
| 826 | dw_i2c_addr = dw_i2c_base_address(bus); |
| 827 | if (!dw_i2c_addr) |
| 828 | return; |
| 829 | |
| 830 | path = acpi_device_path(dev); |
| 831 | if (!path) |
| 832 | return; |
| 833 | |
Tim Wawrzynczak | ba0a393 | 2019-07-17 09:25:59 -0600 | [diff] [blame] | 834 | /* Ensure a default speed is available */ |
| 835 | speed = (bcfg->speed == 0) ? I2C_SPEED_FAST : bcfg->speed; |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 836 | |
Werner Zeh | 1e02ad3 | 2021-05-31 07:08:17 +0200 | [diff] [blame] | 837 | /* Report currently used timing values for the OS driver */ |
| 838 | acpigen_write_scope(path); |
Felix Held | 7edf910 | 2022-01-31 15:56:14 +0100 | [diff] [blame] | 839 | if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) == CB_SUCCESS) { |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 840 | dw_i2c_acpi_write_speed_config(&sgen); |
| 841 | } |
Werner Zeh | 1e02ad3 | 2021-05-31 07:08:17 +0200 | [diff] [blame] | 842 | /* Now check if there are more speed settings available and report them as well. */ |
| 843 | for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) { |
| 844 | if (bcfg->speed_config[i].speed && speed != bcfg->speed_config[i].speed) |
| 845 | dw_i2c_acpi_write_speed_config(&bcfg->speed_config[i]); |
| 846 | } |
| 847 | acpigen_write_scope_end(); |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 848 | } |
| 849 | |
| 850 | static int dw_i2c_dev_transfer(struct device *dev, |
| 851 | const struct i2c_msg *msg, size_t count) |
| 852 | { |
| 853 | return dw_i2c_transfer(dw_i2c_soc_dev_to_bus(dev), msg, count); |
| 854 | } |
| 855 | |
| 856 | const struct i2c_bus_operations dw_i2c_bus_ops = { |
| 857 | .transfer = dw_i2c_dev_transfer, |
| 858 | }; |