blob: 275d56876c3d98a3c61a478b5a9a0dc4b61afc09 [file] [log] [blame]
Ravi Sarawadi91ffac82022-05-07 16:37:09 -07001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <soc/pci_devs.h>
4#include <device/pci_ids.h>
5#include <device/pci_ops.h>
6#include <soc/soc_info.h>
7#include <intelblocks/tcss.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -07008
9uint8_t get_max_usb20_port(void)
10{
Tyler Wang785a7aa2024-03-08 10:39:57 +080011 return CONFIG_SOC_INTEL_USB2_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070012}
13
14uint8_t get_max_usb30_port(void)
15{
Tyler Wang785a7aa2024-03-08 10:39:57 +080016 return CONFIG_SOC_INTEL_USB3_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070017}
18
19uint8_t get_max_tcss_port(void)
20{
Tyler Wang785a7aa2024-03-08 10:39:57 +080021 return MAX_TYPE_C_PORTS;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070022}
23
24uint8_t get_max_tbt_pcie_port(void)
25{
Tyler Wang785a7aa2024-03-08 10:39:57 +080026 return CONFIG_MAX_TBT_ROOT_PORTS;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070027}
28
29uint8_t get_max_pcie_port(void)
30{
Tyler Wang785a7aa2024-03-08 10:39:57 +080031 return CONFIG_MAX_ROOT_PORTS;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070032}
33
34uint8_t get_max_pcie_clock(void)
35{
Tyler Wang785a7aa2024-03-08 10:39:57 +080036 return CONFIG_MAX_PCIE_CLOCK_SRC;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070037}
38
39uint8_t get_max_uart_port(void)
40{
Tyler Wang785a7aa2024-03-08 10:39:57 +080041 return CONFIG_SOC_INTEL_UART_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070042}
43
44uint8_t get_max_i2c_port(void)
45{
Tyler Wang785a7aa2024-03-08 10:39:57 +080046 return CONFIG_SOC_INTEL_I2C_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070047}
48
49uint8_t get_max_gspi_port(void)
50{
Tyler Wang785a7aa2024-03-08 10:39:57 +080051 return CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070052}