blob: 0772c7799b089716a115c3e88f999c2a8e173d2b [file] [log] [blame]
Ravi Sarawadi91ffac82022-05-07 16:37:09 -07001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <soc/pci_devs.h>
4#include <device/pci_ids.h>
5#include <device/pci_ops.h>
6#include <soc/soc_info.h>
7#include <intelblocks/tcss.h>
8#include <console/console.h>
9
10uint8_t get_max_usb20_port(void)
11{
Tyler Wang785a7aa2024-03-08 10:39:57 +080012 return CONFIG_SOC_INTEL_USB2_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070013}
14
15uint8_t get_max_usb30_port(void)
16{
Tyler Wang785a7aa2024-03-08 10:39:57 +080017 return CONFIG_SOC_INTEL_USB3_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070018}
19
20uint8_t get_max_tcss_port(void)
21{
Tyler Wang785a7aa2024-03-08 10:39:57 +080022 return MAX_TYPE_C_PORTS;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070023}
24
25uint8_t get_max_tbt_pcie_port(void)
26{
Tyler Wang785a7aa2024-03-08 10:39:57 +080027 return CONFIG_MAX_TBT_ROOT_PORTS;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070028}
29
30uint8_t get_max_pcie_port(void)
31{
Tyler Wang785a7aa2024-03-08 10:39:57 +080032 return CONFIG_MAX_ROOT_PORTS;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070033}
34
35uint8_t get_max_pcie_clock(void)
36{
Tyler Wang785a7aa2024-03-08 10:39:57 +080037 return CONFIG_MAX_PCIE_CLOCK_SRC;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070038}
39
40uint8_t get_max_uart_port(void)
41{
Tyler Wang785a7aa2024-03-08 10:39:57 +080042 return CONFIG_SOC_INTEL_UART_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070043}
44
45uint8_t get_max_i2c_port(void)
46{
Tyler Wang785a7aa2024-03-08 10:39:57 +080047 return CONFIG_SOC_INTEL_I2C_DEV_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070048}
49
50uint8_t get_max_gspi_port(void)
51{
Tyler Wang785a7aa2024-03-08 10:39:57 +080052 return CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX;
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070053}