Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 4 | #include <fsp/api.h> |
| 5 | #include <soc/romstage.h> |
| 6 | #include <soc/meminit.h> |
Michał Żygowski | 9711248 | 2022-11-09 18:15:51 +0100 | [diff] [blame] | 7 | #include <string.h> |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 8 | |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 9 | #include "gpio.h" |
| 10 | |
Michał Żygowski | 9711248 | 2022-11-09 18:15:51 +0100 | [diff] [blame] | 11 | #define FSP_CLK_NOTUSED 0xFF |
| 12 | #define FSP_CLK_FREE_RUNNING 0x80 |
| 13 | |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 14 | static const struct mb_cfg ddr4_mem_config = { |
| 15 | .type = MEM_TYPE_DDR4, |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 16 | /* According to DOC #573387 rcomp values no longer have to be provided */ |
| 17 | /* DDR DIMM configuration does not need to set DQ/DQS maps */ |
| 18 | .UserBd = BOARD_TYPE_DESKTOP_2DPC, |
| 19 | |
| 20 | .ddr_config = { |
| 21 | .dq_pins_interleaved = true, |
| 22 | }, |
| 23 | }; |
| 24 | |
| 25 | static const struct mb_cfg ddr5_mem_config = { |
| 26 | .type = MEM_TYPE_DDR5, |
| 27 | |
| 28 | .ect = true, /* Early Command Training */ |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 29 | |
Michał Żygowski | 02db6b4 | 2022-04-08 17:12:13 +0200 | [diff] [blame] | 30 | /* According to DOC #573387 rcomp values no longer have to be provided */ |
| 31 | /* DDR DIMM configuration does not need to set DQ/DQS maps */ |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 32 | .UserBd = BOARD_TYPE_DESKTOP_2DPC, |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 33 | |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 34 | .LpDdrDqDqsReTraining = 1, |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 35 | |
| 36 | .ddr_config = { |
Michał Żygowski | 02db6b4 | 2022-04-08 17:12:13 +0200 | [diff] [blame] | 37 | .dq_pins_interleaved = true, |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 38 | }, |
| 39 | }; |
| 40 | |
| 41 | static const struct mem_spd dimm_module_spd_info = { |
| 42 | .topo = MEM_TOPO_DIMM_MODULE, |
| 43 | .smbus = { |
| 44 | [0] = { |
| 45 | .addr_dimm[0] = 0x50, |
| 46 | .addr_dimm[1] = 0x51, |
| 47 | }, |
| 48 | [1] = { |
| 49 | .addr_dimm[0] = 0x52, |
| 50 | .addr_dimm[1] = 0x53, |
| 51 | }, |
| 52 | }, |
| 53 | }; |
| 54 | |
Michał Żygowski | 9711248 | 2022-11-09 18:15:51 +0100 | [diff] [blame] | 55 | static void disable_pcie_clock_requests(FSP_M_CONFIG *m_cfg) |
| 56 | { |
| 57 | memset(m_cfg->PcieClkSrcUsage, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcUsage)); |
| 58 | memset(m_cfg->PcieClkSrcClkReq, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcClkReq)); |
| 59 | |
| 60 | /* PCIe CLK SRCes as per devicetree.cb */ |
| 61 | m_cfg->PcieClkSrcUsage[0] = FSP_CLK_FREE_RUNNING; |
| 62 | m_cfg->PcieClkSrcUsage[8] = FSP_CLK_FREE_RUNNING; |
| 63 | m_cfg->PcieClkSrcUsage[9] = FSP_CLK_FREE_RUNNING; |
| 64 | m_cfg->PcieClkSrcUsage[10] = FSP_CLK_FREE_RUNNING; |
| 65 | m_cfg->PcieClkSrcUsage[12] = FSP_CLK_FREE_RUNNING; |
| 66 | m_cfg->PcieClkSrcUsage[13] = FSP_CLK_FREE_RUNNING; |
| 67 | m_cfg->PcieClkSrcUsage[14] = FSP_CLK_FREE_RUNNING; |
| 68 | m_cfg->PcieClkSrcUsage[15] = FSP_CLK_FREE_RUNNING; |
| 69 | m_cfg->PcieClkSrcUsage[17] = FSP_CLK_FREE_RUNNING; |
| 70 | |
| 71 | gpio_configure_pads(clkreq_disabled_table, ARRAY_SIZE(clkreq_disabled_table)); |
| 72 | } |
| 73 | |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 74 | void mainboard_memory_init_params(FSPM_UPD *memupd) |
| 75 | { |
Michał Żygowski | 9711248 | 2022-11-09 18:15:51 +0100 | [diff] [blame] | 76 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = CONFIG(PCIEXP_CLK_PM); |
| 77 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM); |
| 78 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM); |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 79 | memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented |
Michał Żygowski | cd3a99e | 2022-11-18 17:33:45 +0100 | [diff] [blame] | 80 | memupd->FspmConfig.DmiAspm = 0; |
| 81 | memupd->FspmConfig.DmiAspmCtrl = 0; |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 82 | memupd->FspmConfig.SkipExtGfxScan = 0; |
| 83 | |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 84 | memupd->FspmConfig.PchHdaSdiEnable[0] = 1; |
| 85 | |
Michał Żygowski | 9f87ad2 | 2022-10-15 12:38:35 +0200 | [diff] [blame] | 86 | if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) |
| 87 | memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); |
| 88 | if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) |
| 89 | memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 90 | |
| 91 | gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); |
Michał Żygowski | 9711248 | 2022-11-09 18:15:51 +0100 | [diff] [blame] | 92 | |
| 93 | if (!CONFIG(PCIEXP_CLK_PM)) |
| 94 | disable_pcie_clock_requests(&memupd->FspmConfig); |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 95 | } |