blob: 60f2371dfb009d3b59e8a22f1908512c5def8406 [file] [log] [blame]
Michał Żygowski90989b32022-04-07 15:16:46 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <assert.h>
4#include <console/console.h>
5#include <fsp/api.h>
6#include <soc/romstage.h>
7#include <soc/meminit.h>
8
9static const struct mb_cfg ddr4_mem_config = {
10 .type = MEM_TYPE_DDR4,
11
Michał Żygowski02db6b42022-04-08 17:12:13 +020012 /* According to DOC #573387 rcomp values no longer have to be provided */
13 /* DDR DIMM configuration does not need to set DQ/DQS maps */
Michał Żygowski90989b32022-04-07 15:16:46 +020014
15 .UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */
16
17 .ddr_config = {
Michał Żygowski02db6b42022-04-08 17:12:13 +020018 .dq_pins_interleaved = true,
Michał Żygowski90989b32022-04-07 15:16:46 +020019 },
20};
21
22static const struct mem_spd dimm_module_spd_info = {
23 .topo = MEM_TOPO_DIMM_MODULE,
24 .smbus = {
25 [0] = {
26 .addr_dimm[0] = 0x50,
27 .addr_dimm[1] = 0x51,
28 },
29 [1] = {
30 .addr_dimm[0] = 0x52,
31 .addr_dimm[1] = 0x53,
32 },
33 },
34};
35
36void mainboard_memory_init_params(FSPM_UPD *memupd)
37{
38 memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false);
39}