Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
| 7 | register "pcie_rp0_clkreq_pin" = "0" # wifi/bt |
| 8 | # Disable unused clkreq of PCIe root ports |
| 9 | register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" |
| 10 | register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" |
| 11 | register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" |
| 12 | register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" |
| 13 | register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" |
| 14 | |
| 15 | # GPIO for PERST_0 |
| 16 | # If the Board has PERST_0 signal, assign the GPIO |
| 17 | # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF |
Kevin Chiu | f5fb219 | 2016-11-09 13:48:12 +0800 | [diff] [blame] | 18 | register "prt0_gpio" = "GPIO_122" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 19 | |
| 20 | # EMMC TX DATA Delay 1 |
| 21 | # Refer to EDS-Vol2-22.3. |
| 22 | # [14:8] steps of delay for HS400, each 125ps. |
| 23 | # [6:0] steps of delay for SDR104/HS200, each 125ps. |
| 24 | register "emmc_tx_data_cntl1" = "0x0C16" |
| 25 | |
| 26 | # EMMC TX DATA Delay 2 |
| 27 | # Refer to EDS-Vol2-22.3. |
| 28 | # [30:24] steps of delay for SDR50, each 125ps. |
| 29 | # [22:16] steps of delay for DDR50, each 125ps. |
| 30 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 31 | # [6:0] steps of delay for SDR12, each 125ps. |
| 32 | register "emmc_tx_data_cntl2" = "0x28162828" |
| 33 | |
| 34 | # EMMC RX CMD/DATA Delay 1 |
| 35 | # Refer to EDS-Vol2-22.3. |
| 36 | # [30:24] steps of delay for SDR50, each 125ps. |
| 37 | # [22:16] steps of delay for DDR50, each 125ps. |
| 38 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 39 | # [6:0] steps of delay for SDR12, each 125ps. |
| 40 | register "emmc_rx_cmd_data_cntl1" = "0x00181717" |
| 41 | |
| 42 | # EMMC RX CMD/DATA Delay 2 |
| 43 | # Refer to EDS-Vol2-22.3. |
| 44 | # [17:16] stands for Rx Clock before Output Buffer |
| 45 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps. |
| 46 | # [6:0] steps of delay for HS200, each 125ps. |
| 47 | register "emmc_rx_cmd_data_cntl2" = "0x10008" |
| 48 | |
| 49 | # Enable DPTF |
| 50 | register "dptf_enable" = "1" |
| 51 | |
Kevin Chiu | c4943d8 | 2016-11-09 14:07:30 +0800 | [diff] [blame] | 52 | # PL1 override 12000 mW: the energy calculation is wrong with the |
| 53 | # current VR solution. Experiments show that SoC TDP max (6W) can |
| 54 | # be reached when RAPL PL1 is set to 12W. |
| 55 | register "tdp_pl1_override_mw" = "12000" |
Kevin Chiu | a0f6f9b | 2016-12-09 11:42:05 +0800 | [diff] [blame] | 56 | # Set RAPL PL2 to 15W. |
| 57 | register "tdp_pl2_override_mw" = "15000" |
Kevin Chiu | c4943d8 | 2016-11-09 14:07:30 +0800 | [diff] [blame] | 58 | |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 59 | # Enable Audio Clock and Power gating |
| 60 | register "hdaudio_clk_gate_enable" = "1" |
| 61 | register "hdaudio_pwr_gate_enable" = "1" |
| 62 | register "hdaudio_bios_config_lockdown" = "1" |
| 63 | |
| 64 | # Enable lpss s0ix |
| 65 | register "lpss_s0ix_enable" = "1" |
| 66 | |
| 67 | # GPE configuration |
| 68 | # Note that GPE events called out in ASL code rely on this |
| 69 | # route, i.e., if this route changes then the affected GPE |
| 70 | # offset bits also need to be changed. This sets the PMC register |
| 71 | # GPE_CFG fields. |
| 72 | register "gpe0_dw1" = "PMC_GPE_N_31_0" |
| 73 | register "gpe0_dw2" = "PMC_GPE_N_63_32" |
| 74 | register "gpe0_dw3" = "PMC_GPE_SW_31_0" |
| 75 | |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 76 | # Enable I2C0 for audio codec at 400kHz |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 77 | register "i2c[0]" = "{ |
| 78 | .speed = I2C_SPEED_FAST, |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 79 | .rise_time_ns = 104, |
| 80 | .fall_time_ns = 52, |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 81 | }" |
| 82 | |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 83 | # Enable I2C2 bus early for TPM at 400kHz |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 84 | register "i2c[2]" = "{ |
| 85 | .early_init = 1, |
| 86 | .speed = I2C_SPEED_FAST, |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 87 | .rise_time_ns = 50, |
| 88 | .fall_time_ns = 23, |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 89 | }" |
| 90 | |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 91 | # touchscreen at 400kHz |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 92 | register "i2c[3]" = "{ |
| 93 | .speed = I2C_SPEED_FAST, |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 94 | .rise_time_ns = 76, |
| 95 | .fall_time_ns = 164, |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 96 | }" |
| 97 | |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 98 | # trackpad at 400kHz |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 99 | register "i2c[4]" = "{ |
| 100 | .speed = I2C_SPEED_FAST, |
Kevin Chiu | 35d7d58 | 2016-11-30 16:30:28 +0800 | [diff] [blame] | 101 | .rise_time_ns = 90, |
| 102 | .fall_time_ns = 164, |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 103 | }" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 104 | |
| 105 | # Minimum SLP S3 assertion width 28ms. |
| 106 | register "slp_s3_assertion_width_usecs" = "28000" |
| 107 | |
Kevin Chiu | 0117924 | 2017-01-25 23:06:23 +0800 | [diff] [blame] | 108 | # Override USB2 PER PORT register (PORT 0) |
| 109 | register "usb2eye[0]" = "{ |
| 110 | .Usb20PerPortPeTxiSet = 7, |
| 111 | .Usb20PerPortTxiSet = 1, |
| 112 | .Usb20IUsbTxEmphasisEn = 3, |
| 113 | .Usb20PerPortTxPeHalf = 0, |
| 114 | }" |
| 115 | |
| 116 | # Override USB2 PER PORT register (PORT 1) |
| 117 | register "usb2eye[1]" = "{ |
| 118 | .Usb20PerPortPeTxiSet = 7, |
| 119 | .Usb20PerPortTxiSet = 2, |
| 120 | .Usb20IUsbTxEmphasisEn = 3, |
| 121 | .Usb20PerPortTxPeHalf = 0, |
| 122 | }" |
| 123 | |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 124 | device domain 0 on |
| 125 | device pci 00.0 on end # - Host Bridge |
| 126 | device pci 00.1 on end # - DPTF |
| 127 | device pci 00.2 on end # - NPK |
| 128 | device pci 02.0 on end # - Gen |
| 129 | device pci 03.0 on end # - Iunit |
| 130 | device pci 0d.0 on end # - P2SB |
| 131 | device pci 0d.1 on end # - PMC |
| 132 | device pci 0d.2 on end # - SPI |
| 133 | device pci 0d.3 on end # - Shared SRAM |
| 134 | device pci 0e.0 on # - Audio |
| 135 | chip drivers/generic/max98357a |
Martin Roth | 2e6aeba | 2016-10-07 10:48:31 -0600 | [diff] [blame] | 136 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" |
Kevin Chiu | 49ef5aa | 2016-11-09 14:23:06 +0800 | [diff] [blame] | 137 | register "sdmode_delay" = "5" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 138 | device generic 0 on end |
| 139 | end |
| 140 | end |
| 141 | device pci 11.0 off end # - ISH |
| 142 | device pci 12.0 off end # - SATA |
| 143 | device pci 13.0 off end # - Root Port 2 - PCIe-A 0 |
| 144 | device pci 13.1 off end # - Root Port 3 - PCIe-A 1 |
| 145 | device pci 13.2 off end # - Root Port 4 - PCIe-A 2 |
| 146 | device pci 13.3 off end # - Root Port 5 - PCIe-A 3 |
| 147 | device pci 14.0 on |
| 148 | chip drivers/intel/wifi |
| 149 | register "wake" = "GPE0_DW3_00" |
| 150 | device pci 00.0 on end |
| 151 | end |
| 152 | end # - Root Port 0 - PCIe-B 0 - Wifi |
| 153 | device pci 14.1 off end # - Root Port 1 - PCIe-B 1 |
| 154 | device pci 15.0 on end # - XHCI |
| 155 | device pci 15.1 off end # - XDCI |
| 156 | device pci 16.0 on # - I2C 0 |
| 157 | chip drivers/i2c/da7219 |
| 158 | register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" |
| 159 | register "btn_cfg" = "50" |
| 160 | register "mic_det_thr" = "500" |
| 161 | register "jack_ins_deb" = "20" |
| 162 | register "jack_det_rate" = ""32ms_64ms"" |
| 163 | register "jack_rem_deb" = "1" |
| 164 | register "a_d_btn_thr" = "0xa" |
| 165 | register "d_b_btn_thr" = "0x16" |
| 166 | register "b_c_btn_thr" = "0x21" |
| 167 | register "c_mic_btn_thr" = "0x3e" |
| 168 | register "btn_avg" = "4" |
| 169 | register "adc_1bit_rpt" = "1" |
| 170 | register "micbias_lvl" = "2600" |
| 171 | register "mic_amp_in_sel" = ""diff"" |
| 172 | device i2c 1a on end |
| 173 | end |
| 174 | end |
| 175 | device pci 16.1 on end # - I2C 1 |
| 176 | device pci 16.2 on |
| 177 | chip drivers/i2c/tpm |
| 178 | register "hid" = ""GOOG0005"" |
| 179 | register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" |
| 180 | device i2c 50 on end |
| 181 | end |
| 182 | end # - I2C 2 |
| 183 | device pci 16.3 on |
Furquan Shaikh | 73edd2b | 2016-11-09 10:52:12 -0800 | [diff] [blame] | 184 | chip drivers/i2c/wacom |
Furquan Shaikh | 8be4fdf | 2016-10-21 16:45:59 -0700 | [diff] [blame] | 185 | register "generic" = "{ |
Janice Li | e19c80b | 2016-11-07 17:49:44 +0800 | [diff] [blame] | 186 | .hid = WCOMNTN2_HID, |
Furquan Shaikh | 8be4fdf | 2016-10-21 16:45:59 -0700 | [diff] [blame] | 187 | .cid = PNP0C50_CID, |
| 188 | .desc = WCOM_TS_DESC, |
Kevin Chiu | 84361b1 | 2017-01-24 16:24:30 +0800 | [diff] [blame] | 189 | .irq = IRQ_LEVEL_LOW(GPIO_21_IRQ), |
Kevin Chiu | b576e6f | 2017-02-04 03:55:01 +0800 | [diff] [blame] | 190 | .probed = 1, |
Furquan Shaikh | a7a517d | 2017-01-25 19:15:49 -0800 | [diff] [blame] | 191 | .reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36), |
| 192 | .reset_delay_ms = 20, |
| 193 | .enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152), |
| 194 | .enable_delay_ms = 1, |
| 195 | .has_power_resource = 1, |
| 196 | .disable_gpio_export_in_crs = 1, |
Furquan Shaikh | 8be4fdf | 2016-10-21 16:45:59 -0700 | [diff] [blame] | 197 | }" |
| 198 | register "hid_desc_reg_offset" = "0x1" |
| 199 | device i2c 0xA on end |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 200 | end |
Kevin Chiu | 5aadea9 | 2017-01-10 22:31:05 +0800 | [diff] [blame] | 201 | chip drivers/i2c/generic |
| 202 | register "hid" = ""ELAN0001"" |
| 203 | register "desc" = ""ELAN Touchscreen"" |
| 204 | register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" |
| 205 | register "probed" = "1" |
Furquan Shaikh | a7a517d | 2017-01-25 19:15:49 -0800 | [diff] [blame] | 206 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" |
| 207 | register "reset_delay_ms" = "20" |
| 208 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" |
| 209 | register "enable_delay_ms" = "1" |
| 210 | register "has_power_resource" = "1" |
Kevin Chiu | 5aadea9 | 2017-01-10 22:31:05 +0800 | [diff] [blame] | 211 | device i2c 10 on end |
| 212 | end |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 213 | end # - I2C 3 |
| 214 | device pci 17.0 on |
| 215 | chip drivers/i2c/generic |
| 216 | register "hid" = ""ELAN0000"" |
| 217 | register "desc" = ""ELAN Touchpad"" |
| 218 | register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" |
| 219 | register "wake" = "GPE0_DW1_15" |
| 220 | register "probed" = "1" |
| 221 | device i2c 15 on end |
| 222 | end |
| 223 | end # - I2C 4 |
Kevin Chiu | ca38753 | 2016-11-23 18:06:39 +0800 | [diff] [blame] | 224 | device pci 17.1 off end # - I2C 5 |
| 225 | device pci 17.2 off end # - I2C 6 |
| 226 | device pci 17.3 off end # - I2C 7 |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 227 | device pci 18.0 on end # - UART 0 |
| 228 | device pci 18.1 on end # - UART 1 |
| 229 | device pci 18.2 on end # - UART 2 |
Kevin Chiu | ca38753 | 2016-11-23 18:06:39 +0800 | [diff] [blame] | 230 | device pci 18.3 off end # - UART 3 |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 231 | device pci 19.0 on end # - SPI 0 |
Kevin Chiu | ca38753 | 2016-11-23 18:06:39 +0800 | [diff] [blame] | 232 | device pci 19.1 off end # - SPI 1 |
| 233 | device pci 19.2 off end # - SPI 2 |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 234 | device pci 1a.0 on end # - PWM |
| 235 | device pci 1b.0 on end # - SDCARD |
| 236 | device pci 1c.0 on end # - eMMC |
| 237 | device pci 1e.0 off end # - SDIO |
| 238 | device pci 1f.0 on # - LPC |
| 239 | chip ec/google/chromeec |
| 240 | device pnp 0c09.0 on end |
| 241 | end |
| 242 | end |
| 243 | device pci 1f.1 on end # - SMBUS |
| 244 | end |
| 245 | end |