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review.coreboot.org / coreboot / 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d / . / src / mainboard / ibase / mb899 / mptable.c
blob: 0ada84d7bb1faa233f8ce61f51ecf38c6e55be6f [file] [log] [blame]
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]20#include <device/device.h>
21#include <device/pci.h>
22#include <console/console.h>
23#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]24#include <arch/ioapic.h>
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]25#include <string.h>
26#include <stdint.h>
27
28static void *smp_write_config_table(void *v)
29{
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]30 struct mp_config_table *mc;
31 struct device *riser = NULL, *firewire = NULL;
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame^]32 int firewire_bus = 0, riser_bus = 0, isa_bus;
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]33 int ioapic_id;
34
35 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]36
Uwe Hermann55dc2232010-10-25 15:32:07 +0000[diff] [blame]37 mptable_init(mc, "MB899 ", LAPIC_ADDR);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]38
39 smp_write_processors(mc);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]40
41 firewire = dev_find_device(0x104c, 0x8023, 0);
42 if (firewire) {
43 firewire_bus = firewire->bus->secondary;
44 printk(BIOS_SPEW, "Firewire device is on bus %x\n",
45 firewire_bus);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]46 }
47
48 // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
49 // highest bus number on the pci bus.
50 riser = dev_find_device(0x3388, 0x0021, 0);
51 if (!riser)
52 riser = dev_find_device(0x3388, 0x0022, 0);
53 if (riser) {
Myles Watson894a3472010-06-09 22:41:35 +0000[diff] [blame]54 riser_bus = riser->link_list->secondary;
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]55 printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]56 }
57
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame^]58 mptable_write_buses(mc, NULL, &isa_bus);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]59
60 /* I/O APICs: APIC ID Version State Address */
61 ioapic_id = 2;
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]62 smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]63
64 /* Legacy Interrupts */
65
66 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
67 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
69 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
70 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
71 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
73 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
75 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
80
81 /* Builtin devices on Bus 0 */
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
91 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
92
93 /* Internal PCI bus (Firewire, PCI slot) */
94 if (firewire) {
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
97 }
98
99 if (riser) {
100 /* Old riser card */
101 // riser slot top 5:8.0
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
103 // riser slot middle 5:9.0
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
105 // riser slot bottom 5:a.0
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
107
108 /* New Riser Card */
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
112 }
113
114 /* PCIe slot */
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
117
118 /* Onboard Ethernet */
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
120
121 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Tobias Diedrichb907d322010-10-26 22:40:16 +0000[diff] [blame]122 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
123 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]124
125 /* Compute the checksums */
126 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
127 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
128
129 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
130
131 return smp_next_mpe_entry(mc);
132}
133
134/* MP table generation in coreboot is not very well designed;
135 * One of the issues is that it knows nothing about Virtual
136 * Wire mode, which everyone uses since a decade or so. This
137 * function fixes up our floating table. This spares us doing
138 * a half-baked fix of adding a new parameter to 200+ calls
139 * to smp_write_floating_table()
140 */
141static void fixup_virtual_wire(void *v)
142{
143 struct intel_mp_floating *mf = v;
144
145 mf->mpf_checksum = 0;
146 mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
147 mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
148}
149
150unsigned long write_smp_table(unsigned long addr)
151{
152 void *v;
153 v = smp_write_floating_table(addr);
154 fixup_virtual_wire(v);
155 return (unsigned long)smp_write_config_table(v);
156}