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review.coreboot.org / coreboot / 8cda9699d4a2fea8ed2c5e4a7e66e8e1e0f831df / . / src / mainboard / ibase / mb899 / mptable.c
blob: 0d05638e39bc29384ef61fd8acd6f19c87cac5a8 [file] [log] [blame]
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]20#include <device/device.h>
21#include <device/pci.h>
22#include <console/console.h>
23#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]24#include <arch/ioapic.h>
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]25#include <string.h>
26#include <stdint.h>
27
28static void *smp_write_config_table(void *v)
29{
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]30 struct mp_config_table *mc;
31 struct device *riser = NULL, *firewire = NULL;
32 int i;
33 int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
34 int ioapic_id;
35
36 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]37
Uwe Hermann55dc2232010-10-25 15:32:07 +0000[diff] [blame]38 mptable_init(mc, "MB899 ", LAPIC_ADDR);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]39
40 smp_write_processors(mc);
41 max_pci_bus=0;
42
43 firewire = dev_find_device(0x104c, 0x8023, 0);
44 if (firewire) {
45 firewire_bus = firewire->bus->secondary;
46 printk(BIOS_SPEW, "Firewire device is on bus %x\n",
47 firewire_bus);
48 max_pci_bus = firewire_bus;
49 }
50
51 // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
52 // highest bus number on the pci bus.
53 riser = dev_find_device(0x3388, 0x0021, 0);
54 if (!riser)
55 riser = dev_find_device(0x3388, 0x0022, 0);
56 if (riser) {
Myles Watson894a3472010-06-09 22:41:35 +0000[diff] [blame]57 riser_bus = riser->link_list->secondary;
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]58 printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
59 max_pci_bus = riser_bus;
60 }
61
62 /* ISA bus follows */
63 isa_bus = max_pci_bus + 1;
64
65 /* Bus: Bus ID Type */
66 for (i=0; i <= max_pci_bus; i++)
67 smp_write_bus(mc, i, "PCI ");
68
69 smp_write_bus(mc, isa_bus, "ISA ");
70
71 /* I/O APICs: APIC ID Version State Address */
72 ioapic_id = 2;
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]73 smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]74
75 /* Legacy Interrupts */
76
77 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
78 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
85 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
91
92 /* Builtin devices on Bus 0 */
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
101 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
103
104 /* Internal PCI bus (Firewire, PCI slot) */
105 if (firewire) {
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
108 }
109
110 if (riser) {
111 /* Old riser card */
112 // riser slot top 5:8.0
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
114 // riser slot middle 5:9.0
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
116 // riser slot bottom 5:a.0
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
118
119 /* New Riser Card */
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
123 }
124
125 /* PCIe slot */
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
128
129 /* Onboard Ethernet */
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
131
132 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Tobias Diedrichb907d322010-10-26 22:40:16 +0000[diff] [blame]133 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
134 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]135
136 /* Compute the checksums */
137 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
138 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
139
140 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
141
142 return smp_next_mpe_entry(mc);
143}
144
145/* MP table generation in coreboot is not very well designed;
146 * One of the issues is that it knows nothing about Virtual
147 * Wire mode, which everyone uses since a decade or so. This
148 * function fixes up our floating table. This spares us doing
149 * a half-baked fix of adding a new parameter to 200+ calls
150 * to smp_write_floating_table()
151 */
152static void fixup_virtual_wire(void *v)
153{
154 struct intel_mp_floating *mf = v;
155
156 mf->mpf_checksum = 0;
157 mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
158 mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
159}
160
161unsigned long write_smp_table(unsigned long addr)
162{
163 void *v;
164 v = smp_write_floating_table(addr);
165 fixup_virtual_wire(v);
166 return (unsigned long)smp_write_config_table(v);
167}