Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 18 | */ |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 19 | |
Kyösti Mälkki | 526c2fb | 2014-07-10 22:16:58 +0300 | [diff] [blame] | 20 | #include "AGESA.h" |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 21 | #include "amdlib.h" |
| 22 | #include "BiosCallOuts.h" |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 23 | #include "heapManager.h" |
| 24 | #include "SB800.h" |
Kyösti Mälkki | 50c9637 | 2014-10-18 07:51:03 +0300 | [diff] [blame^] | 25 | #include <southbridge/amd/cimx/sb800/gpio_oem.h> |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 26 | #include <stdlib.h> |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 27 | |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 28 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); |
| 29 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); |
| 30 | |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 31 | const BIOS_CALLOUT_STRUCT BiosCallouts[] = |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 32 | { |
Kyösti Mälkki | ef9343c | 2014-05-04 11:42:55 +0300 | [diff] [blame] | 33 | {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, |
| 34 | {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, |
| 35 | {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, |
Kyösti Mälkki | 5e19fa4 | 2014-05-04 23:13:54 +0300 | [diff] [blame] | 36 | {AGESA_DO_RESET, agesa_Reset }, |
Kyösti Mälkki | a1ebbc4 | 2014-10-17 22:33:22 +0300 | [diff] [blame] | 37 | {AGESA_READ_SPD, agesa_ReadSpd }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 38 | {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, |
Kyösti Mälkki | 6b4b151 | 2014-05-05 12:05:53 +0300 | [diff] [blame] | 39 | {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 40 | {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, |
| 41 | {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, |
Kyösti Mälkki | c459f96 | 2014-05-04 17:07:45 +0300 | [diff] [blame] | 42 | {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, |
| 43 | {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, |
| 44 | {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 45 | }; |
Kyösti Mälkki | 6025efa | 2014-05-05 13:20:56 +0300 | [diff] [blame] | 46 | const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 47 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 48 | /* Call the host environment interface to provide a user hook opportunity. */ |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 49 | static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 50 | { |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 51 | AGESA_STATUS Status; |
| 52 | UINTN FcnData; |
| 53 | MEM_DATA_STRUCT *MemData; |
| 54 | UINT32 AcpiMmioAddr; |
| 55 | UINT32 GpioMmioAddr; |
| 56 | UINT8 Data8; |
| 57 | UINT16 Data16; |
| 58 | UINT8 TempData8; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 59 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 60 | FcnData = Data; |
| 61 | MemData = ConfigPtr; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 62 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 63 | Status = AGESA_SUCCESS; |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 64 | /* Get SB MMIO Base (AcpiMmioAddr) */ |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 65 | WriteIo8 (0xCD6, 0x27); |
| 66 | Data8 = ReadIo8(0xCD7); |
| 67 | Data16 = Data8<<8; |
| 68 | WriteIo8 (0xCD6, 0x26); |
| 69 | Data8 = ReadIo8(0xCD7); |
| 70 | Data16 |= Data8; |
| 71 | AcpiMmioAddr = (UINT32)Data16 << 16; |
| 72 | GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 73 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 74 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); |
| 75 | Data8 &= ~BIT5; |
| 76 | TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 77 | TempData8 &= 0x03; |
| 78 | TempData8 |= Data8; |
| 79 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 80 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 81 | Data8 |= BIT2+BIT3; |
| 82 | Data8 &= ~BIT4; |
| 83 | TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 84 | TempData8 &= 0x23; |
| 85 | TempData8 |= Data8; |
| 86 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 87 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 88 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); |
| 89 | Data8 &= ~BIT5; |
| 90 | TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); |
| 91 | TempData8 &= 0x03; |
| 92 | TempData8 |= Data8; |
| 93 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 94 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 95 | Data8 |= BIT2+BIT3; |
| 96 | Data8 &= ~BIT4; |
| 97 | TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); |
| 98 | TempData8 &= 0x23; |
| 99 | TempData8 |= Data8; |
| 100 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 101 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 102 | switch(MemData->ParameterListPtr->DDR3Voltage){ |
| 103 | case VOLT1_35: |
| 104 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 105 | Data8 &= ~(UINT8)BIT6; |
| 106 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); |
| 107 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); |
| 108 | Data8 |= (UINT8)BIT6; |
| 109 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); |
| 110 | break; |
| 111 | case VOLT1_25: |
| 112 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 113 | Data8 &= ~(UINT8)BIT6; |
| 114 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); |
| 115 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); |
| 116 | Data8 &= ~(UINT8)BIT6; |
| 117 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); |
| 118 | break; |
| 119 | case VOLT1_5: |
| 120 | default: |
| 121 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); |
| 122 | Data8 |= (UINT8)BIT6; |
| 123 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); |
| 124 | Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); |
| 125 | Data8 &= ~(UINT8)BIT6; |
| 126 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); |
| 127 | } |
| 128 | return Status; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 129 | } |
Kerry Sheh | 01f7ab9 | 2012-01-19 13:18:36 +0800 | [diff] [blame] | 130 | |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 131 | /* PCIE slot reset control */ |
Kyösti Mälkki | c009601 | 2014-05-05 18:56:33 +0300 | [diff] [blame] | 132 | static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 133 | { |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 134 | AGESA_STATUS Status; |
| 135 | UINTN FcnData; |
| 136 | PCIe_SLOT_RESET_INFO *ResetInfo; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 137 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 138 | UINT32 GpioMmioAddr; |
| 139 | UINT32 AcpiMmioAddr; |
| 140 | UINT8 Data8; |
| 141 | UINT16 Data16; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 142 | |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 143 | FcnData = Data; |
| 144 | ResetInfo = ConfigPtr; |
| 145 | // Get SB800 MMIO Base (AcpiMmioAddr) |
| 146 | WriteIo8(0xCD6, 0x27); |
| 147 | Data8 = ReadIo8(0xCD7); |
| 148 | Data16=Data8<<8; |
| 149 | WriteIo8(0xCD6, 0x26); |
| 150 | Data8 = ReadIo8(0xCD7); |
| 151 | Data16|=Data8; |
| 152 | AcpiMmioAddr = (UINT32)Data16 << 16; |
| 153 | Status = AGESA_UNSUPPORTED; |
| 154 | GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; |
| 155 | switch (ResetInfo->ResetId) |
| 156 | { |
| 157 | case 4: |
| 158 | switch (ResetInfo->ResetControl) { |
| 159 | case AssertSlotReset: |
| 160 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); |
| 161 | Data8 &= ~(UINT8)BIT6 ; |
| 162 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 |
| 163 | Status = AGESA_SUCCESS; |
| 164 | break; |
| 165 | case DeassertSlotReset: |
| 166 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); |
| 167 | Data8 |= BIT6 ; |
| 168 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 |
| 169 | Status = AGESA_SUCCESS; |
| 170 | break; |
| 171 | } |
| 172 | break; |
| 173 | case 6: |
| 174 | switch (ResetInfo->ResetControl) { |
| 175 | case AssertSlotReset: |
| 176 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); |
| 177 | Data8 &= ~(UINT8)BIT6 ; |
| 178 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 |
| 179 | Status = AGESA_SUCCESS; |
| 180 | break; |
| 181 | case DeassertSlotReset: |
| 182 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); |
| 183 | Data8 |= BIT6 ; |
| 184 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 |
| 185 | Status = AGESA_SUCCESS; |
| 186 | break; |
| 187 | } |
| 188 | break; |
| 189 | case 7: |
| 190 | switch (ResetInfo->ResetControl) { |
| 191 | case AssertSlotReset: |
| 192 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); |
| 193 | Data8 &= ~(UINT8)BIT6 ; |
| 194 | Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 |
| 195 | Status = AGESA_SUCCESS; |
| 196 | break; |
| 197 | case DeassertSlotReset: |
Jens Rottmann | f87855c | 2013-02-18 18:56:48 +0100 | [diff] [blame] | 198 | Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); |
Kerry Sheh | f03360f | 2012-01-19 13:25:55 +0800 | [diff] [blame] | 199 | Data8 |= BIT6 ; |
| 200 | Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 |
| 201 | Status = AGESA_SUCCESS; |
| 202 | break; |
| 203 | } |
| 204 | break; |
| 205 | } |
| 206 | return Status; |
Frank Vibrans | 69da1b6 | 2011-02-14 19:04:45 +0000 | [diff] [blame] | 207 | } |