Angel Pons | b5a2a52 | 2020-04-05 13:21:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 2 | |
Simon Glass | b5c5177 | 2018-03-05 12:18:40 -0700 | [diff] [blame] | 3 | #include <string.h> |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 7 | #include <acpi/acpi.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 8 | #include <amdblocks/agesawrapper.h> |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 9 | #include <amdblocks/amd_pci_util.h> |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 10 | #include <amdblocks/i2c.h> |
Martin Roth | b77bc6f | 2017-11-11 14:33:47 -0700 | [diff] [blame] | 11 | #include <baseboard/variants.h> |
Marc Jones | 71f7f0a | 2017-11-21 23:29:55 -0700 | [diff] [blame] | 12 | #include <boardid.h> |
Simon Glass | b5c5177 | 2018-03-05 12:18:40 -0700 | [diff] [blame] | 13 | #include <smbios.h> |
Richard Spiegel | 9dc5600 | 2017-12-18 16:25:42 -0700 | [diff] [blame] | 14 | #include <soc/pci_devs.h> |
Marc Jones | df6b51b | 2017-11-29 20:07:46 -0700 | [diff] [blame] | 15 | #include <soc/southbridge.h> |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 16 | #include <amdblocks/acpimmio.h> |
Martin Roth | 6c623ca | 2017-11-16 22:14:53 -0700 | [diff] [blame] | 17 | #include <variant/ec.h> |
Marc Jones | 067031e | 2017-11-02 11:36:53 -0600 | [diff] [blame] | 18 | #include <variant/thermal.h> |
Marc Jones | 0a15ed5 | 2017-06-22 22:22:20 -0600 | [diff] [blame] | 19 | #include <vendorcode/google/chromeos/chromeos.h> |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 20 | |
| 21 | /*********************************************************** |
| 22 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 23 | * This table is responsible for physically routing the PIC and |
| 24 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 25 | * is read and written via registers 0xC00/0xC01 as an |
| 26 | * Index/Data pair. These values are chipset and mainboard |
| 27 | * dependent and should be updated accordingly. |
| 28 | * |
| 29 | * These values are used by the PCI configuration space, |
| 30 | * MP Tables. TODO: Make ACPI use these values too. |
| 31 | */ |
Martin Roth | 6c14cd3 | 2018-01-11 16:25:28 -0800 | [diff] [blame] | 32 | |
Kyösti Mälkki | e1e3289 | 2019-12-22 09:49:56 +0200 | [diff] [blame] | 33 | static const u8 mainboard_picr_data[] = { |
Martin Roth | 6c14cd3 | 2018-01-11 16:25:28 -0800 | [diff] [blame] | 34 | [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, |
| 35 | [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, |
Richard Spiegel | 8f825e0 | 2018-02-12 08:36:10 -0700 | [diff] [blame] | 36 | [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, |
Martin Roth | 6c14cd3 | 2018-01-11 16:25:28 -0800 | [diff] [blame] | 37 | [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 38 | [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, |
| 39 | [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 40 | [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, |
| 41 | [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
Richard Spiegel | 8f825e0 | 2018-02-12 08:36:10 -0700 | [diff] [blame] | 42 | [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
Martin Roth | 6c14cd3 | 2018-01-11 16:25:28 -0800 | [diff] [blame] | 43 | [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 44 | [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, |
| 45 | [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, |
| 46 | [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, |
| 47 | [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, |
| 48 | [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, |
| 49 | [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, |
| 50 | }; |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 51 | |
Kyösti Mälkki | e1e3289 | 2019-12-22 09:49:56 +0200 | [diff] [blame] | 52 | static const u8 mainboard_intr_data[] = { |
Martin Roth | 6c14cd3 | 2018-01-11 16:25:28 -0800 | [diff] [blame] | 53 | [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17, |
| 54 | [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, |
| 55 | [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, |
| 56 | [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 57 | [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, |
| 58 | [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 59 | [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, |
| 60 | [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 61 | [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 62 | [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 63 | [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, |
| 64 | [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 65 | [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 66 | [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 67 | [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, |
| 68 | [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
| 69 | }; |
Richard Spiegel | 9dc5600 | 2017-12-18 16:25:42 -0700 | [diff] [blame] | 70 | |
| 71 | /* |
| 72 | * This table defines the index into the picr/intr_data tables for each |
| 73 | * device. Any enabled device and slot that uses hardware interrupts should |
| 74 | * have an entry in this table to define its index into the FCH PCI_INTR |
| 75 | * register 0xC00/0xC01. This index will define the interrupt that it should |
| 76 | * use. Putting PIRQ_A into the PIN A index for a device will tell that |
| 77 | * device to use PIC IRQ 10 if it uses PIN A for its hardware INT. |
| 78 | */ |
| 79 | static const struct pirq_struct mainboard_pirq_data[] = { |
| 80 | { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, |
| 81 | { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } }, |
| 82 | { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } }, |
| 83 | { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } }, |
| 84 | { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, |
| 85 | { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } }, |
| 86 | { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, |
| 87 | { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, |
| 88 | { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, |
| 89 | { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, |
| 90 | { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, |
| 91 | }; |
| 92 | |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 93 | /* PIRQ Setup */ |
| 94 | static void pirq_setup(void) |
| 95 | { |
Richard Spiegel | 9dc5600 | 2017-12-18 16:25:42 -0700 | [diff] [blame] | 96 | pirq_data_ptr = mainboard_pirq_data; |
| 97 | pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 98 | intr_data_ptr = mainboard_intr_data; |
| 99 | picr_data_ptr = mainboard_picr_data; |
| 100 | } |
| 101 | |
Kevin Chiu | fb79603 | 2021-03-22 19:34:30 +0800 | [diff] [blame] | 102 | void __weak variant_devtree_update(void) |
| 103 | { |
| 104 | /* Override dev tree settings per board */ |
| 105 | } |
| 106 | |
Marc Jones | 9ad593b | 2017-06-22 22:19:55 -0600 | [diff] [blame] | 107 | static void mainboard_init(void *chip_info) |
| 108 | { |
Marc Jones | 71f7f0a | 2017-11-21 23:29:55 -0700 | [diff] [blame] | 109 | int boardid = board_id(); |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 110 | size_t num_gpios; |
Richard Spiegel | 6fcb9b0 | 2018-04-18 08:06:33 -0700 | [diff] [blame] | 111 | const struct soc_amd_gpio *gpios; |
Marc Jones | 71f7f0a | 2017-11-21 23:29:55 -0700 | [diff] [blame] | 112 | |
| 113 | printk(BIOS_INFO, "Board ID: %d\n", boardid); |
Marc Jones | b6ac3a2 | 2017-10-05 21:57:33 -0600 | [diff] [blame] | 114 | |
Marc Jones | 9ad593b | 2017-06-22 22:19:55 -0600 | [diff] [blame] | 115 | mainboard_ec_init(); |
Marc Jones | b6ac3a2 | 2017-10-05 21:57:33 -0600 | [diff] [blame] | 116 | |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 117 | gpios = variant_gpio_table(&num_gpios); |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 118 | gpio_configure_pads(gpios, num_gpios); |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 119 | |
Daniel Kurtz | f5e3775 | 2018-02-01 15:58:40 -0700 | [diff] [blame] | 120 | /* Initialize i2c busses that were not initialized in bootblock */ |
| 121 | i2c_soc_init(); |
| 122 | |
Martin Roth | 6c14cd3 | 2018-01-11 16:25:28 -0800 | [diff] [blame] | 123 | /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */ |
Martin Roth | b250b23 | 2018-06-02 21:30:21 -0600 | [diff] [blame] | 124 | pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); |
Simon Glass | 4f16049 | 2018-05-23 15:34:04 -0600 | [diff] [blame] | 125 | |
| 126 | /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ |
Kyösti Mälkki | 5b672d5 | 2019-11-25 21:23:37 +0200 | [diff] [blame] | 127 | clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL, |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 128 | GPP_CLK2_REQ_MAP_MASK, |
| 129 | GPP_CLK2_REQ_MAP_CLK_REQ2 << |
| 130 | GPP_CLK2_REQ_MAP_SHIFT); |
Simon Glass | e577168 | 2018-07-11 15:51:27 -0600 | [diff] [blame] | 131 | |
| 132 | /* Same for the WiFi */ |
Kyösti Mälkki | 5b672d5 | 2019-11-25 21:23:37 +0200 | [diff] [blame] | 133 | clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL, |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 134 | GPP_CLK0_REQ_MAP_MASK, |
| 135 | GPP_CLK0_REQ_MAP_CLK_REQ0 << |
| 136 | GPP_CLK0_REQ_MAP_SHIFT); |
Kevin Chiu | fb79603 | 2021-03-22 19:34:30 +0800 | [diff] [blame] | 137 | |
| 138 | variant_devtree_update(); |
Marc Jones | 9ad593b | 2017-06-22 22:19:55 -0600 | [diff] [blame] | 139 | } |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 140 | |
| 141 | /************************************************* |
Marshall Dawson | beb1288 | 2017-05-23 18:57:47 -0600 | [diff] [blame] | 142 | * Dedicated mainboard function |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 143 | *************************************************/ |
Kyösti Mälkki | 813b2f0 | 2021-02-22 06:03:08 +0200 | [diff] [blame] | 144 | static void mainboard_enable(struct device *dev) |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 145 | { |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 146 | /* Initialize the PIRQ data structures for consumption */ |
| 147 | pirq_setup(); |
Marc Jones | 0a15ed5 | 2017-06-22 22:22:20 -0600 | [diff] [blame] | 148 | |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 149 | dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 150 | } |
| 151 | |
Marc Jones | df6b51b | 2017-11-29 20:07:46 -0700 | [diff] [blame] | 152 | int mainboard_get_xhci_oc_map(uint16_t *map) |
| 153 | { |
| 154 | return variant_get_xhci_oc_map(map); |
| 155 | } |
| 156 | |
| 157 | int mainboard_get_ehci_oc_map(uint16_t *map) |
| 158 | { |
| 159 | return variant_get_ehci_oc_map(map); |
| 160 | } |
| 161 | |
Marc Jones | f3dc659 | 2018-07-14 17:27:35 -0600 | [diff] [blame] | 162 | void mainboard_suspend_resume(void) |
| 163 | { |
| 164 | variant_mainboard_suspend_resume(); |
| 165 | } |
Marc Jones | f3dc659 | 2018-07-14 17:27:35 -0600 | [diff] [blame] | 166 | |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 167 | struct chip_operations mainboard_ops = { |
Marc Jones | 9ad593b | 2017-06-22 22:19:55 -0600 | [diff] [blame] | 168 | .init = mainboard_init, |
Kyösti Mälkki | 813b2f0 | 2021-02-22 06:03:08 +0200 | [diff] [blame] | 169 | .enable_dev = mainboard_enable, |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 170 | }; |
Simon Glass | b5c5177 | 2018-03-05 12:18:40 -0700 | [diff] [blame] | 171 | |
Marc Jones | f3dc659 | 2018-07-14 17:27:35 -0600 | [diff] [blame] | 172 | /* Variants may override these functions so see definitions in variants/ */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 173 | uint8_t __weak variant_board_sku(void) |
Simon Glass | b5c5177 | 2018-03-05 12:18:40 -0700 | [diff] [blame] | 174 | { |
| 175 | return 0; |
| 176 | } |
| 177 | |
Marc Jones | f3dc659 | 2018-07-14 17:27:35 -0600 | [diff] [blame] | 178 | void __weak variant_mainboard_suspend_resume(void) |
| 179 | { |
| 180 | } |
Marc Jones | f3dc659 | 2018-07-14 17:27:35 -0600 | [diff] [blame] | 181 | |
Nico Huber | ebd8a4f | 2017-11-01 09:49:16 +0100 | [diff] [blame] | 182 | const char *smbios_system_sku(void) |
Simon Glass | b5c5177 | 2018-03-05 12:18:40 -0700 | [diff] [blame] | 183 | { |
| 184 | static char sku_str[7]; /* sku{0..255} */ |
| 185 | |
| 186 | snprintf(sku_str, sizeof(sku_str), "sku%d", variant_board_sku()); |
| 187 | |
| 188 | return sku_str; |
| 189 | } |