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Marc Jones2d79f162017-05-22 21:35:16 -06001/*
2 * This file is part of the coreboot project.
3 *
Marshall Dawsonbeb12882017-05-23 18:57:47 -06004 * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
Marc Jones2d79f162017-05-22 21:35:16 -06005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <console/console.h>
17#include <device/device.h>
18#include <arch/acpi.h>
Richard Spiegel0ad74ac2017-12-08 16:53:29 -070019#include <amdblocks/agesawrapper.h>
Richard Spiegel2bbc3dc2017-12-06 16:14:58 -070020#include <amdblocks/amd_pci_util.h>
Marc Jones067031e2017-11-02 11:36:53 -060021#include <cbmem.h>
Martin Rothb77bc6f2017-11-11 14:33:47 -070022#include <baseboard/variants.h>
Marc Jones71f7f0a2017-11-21 23:29:55 -070023#include <boardid.h>
Marc Jones067031e2017-11-02 11:36:53 -060024#include <soc/nvs.h>
Richard Spiegel9dc56002017-12-18 16:25:42 -070025#include <soc/pci_devs.h>
Marc Jonesb6ac3a22017-10-05 21:57:33 -060026#include <soc/smi.h>
Marc Jonesdf6b51b2017-11-29 20:07:46 -070027#include <soc/southbridge.h>
Martin Roth6c623ca2017-11-16 22:14:53 -070028#include <variant/ec.h>
Marc Jones067031e2017-11-02 11:36:53 -060029#include <variant/thermal.h>
Marc Jones0a15ed52017-06-22 22:22:20 -060030#include <vendorcode/google/chromeos/chromeos.h>
Marc Jones2d79f162017-05-22 21:35:16 -060031
32/***********************************************************
33 * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
34 * This table is responsible for physically routing the PIC and
35 * IOAPIC IRQs to the different PCI devices on the system. It
36 * is read and written via registers 0xC00/0xC01 as an
37 * Index/Data pair. These values are chipset and mainboard
38 * dependent and should be updated accordingly.
39 *
40 * These values are used by the PCI configuration space,
41 * MP Tables. TODO: Make ACPI use these values too.
42 */
Martin Roth6c14cd32018-01-11 16:25:28 -080043
44// TODO: Move these to board variant specific file
45#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)
Marc Jones2d79f162017-05-22 21:35:16 -060046const u8 mainboard_picr_data[] = {
47 [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
48 [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
49 [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
50 [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
51 [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
52 [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
53 [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
54 [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
55 [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
56 [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
57 [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
58 [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
59 [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
60 [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
61 [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
62 [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
63};
64
65const u8 mainboard_intr_data[] = {
66 [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
67 [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
68 [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
69 [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
70 [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
71 [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
73 [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
74 [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75 [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
76 [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
77 [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
78 [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
79 [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
80 [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
81 [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
82};
Martin Roth6c14cd32018-01-11 16:25:28 -080083#else
84const u8 mainboard_picr_data[] = {
85 [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F,
86 [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
87 [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
88 [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
90 [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91 [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
92 [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93 [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
94 [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
95 [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
96 [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
97 [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
98 [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
99 [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
100 [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
101};
Marc Jones2d79f162017-05-22 21:35:16 -0600102
Martin Roth6c14cd32018-01-11 16:25:28 -0800103const u8 mainboard_intr_data[] = {
104 [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17,
105 [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
106 [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
107 [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
108 [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
109 [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
110 [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
111 [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
112 [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
113 [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
114 [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
115 [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
116 [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
117 [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
118 [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
119 [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
120};
121#endif
Richard Spiegel9dc56002017-12-18 16:25:42 -0700122
123/*
124 * This table defines the index into the picr/intr_data tables for each
125 * device. Any enabled device and slot that uses hardware interrupts should
126 * have an entry in this table to define its index into the FCH PCI_INTR
127 * register 0xC00/0xC01. This index will define the interrupt that it should
128 * use. Putting PIRQ_A into the PIN A index for a device will tell that
129 * device to use PIC IRQ 10 if it uses PIN A for its hardware INT.
130 */
131static const struct pirq_struct mainboard_pirq_data[] = {
132 { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
133 { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } },
134 { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } },
135 { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } },
136 { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
137 { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } },
138 { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
139 { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
140 { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
141 { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
142 { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
143};
144
Marc Jones2d79f162017-05-22 21:35:16 -0600145/* PIRQ Setup */
146static void pirq_setup(void)
147{
Richard Spiegel9dc56002017-12-18 16:25:42 -0700148 pirq_data_ptr = mainboard_pirq_data;
149 pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
Marc Jones2d79f162017-05-22 21:35:16 -0600150 intr_data_ptr = mainboard_intr_data;
151 picr_data_ptr = mainboard_picr_data;
152}
153
Marc Jones9ad593b2017-06-22 22:19:55 -0600154static void mainboard_init(void *chip_info)
155{
Marc Jonesb6ac3a22017-10-05 21:57:33 -0600156 const struct sci_source *gpes;
157 size_t num;
Marc Jones71f7f0a2017-11-21 23:29:55 -0700158 int boardid = board_id();
159
160 printk(BIOS_INFO, "Board ID: %d\n", boardid);
Marc Jonesb6ac3a22017-10-05 21:57:33 -0600161
Marc Jones9ad593b2017-06-22 22:19:55 -0600162 mainboard_ec_init();
Marc Jonesb6ac3a22017-10-05 21:57:33 -0600163
164 gpes = get_gpe_table(&num);
165 gpe_configure_sci(gpes, num);
Martin Roth6c14cd32018-01-11 16:25:28 -0800166
167 /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
168 if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE))
169 pm_write8(PM_PCIB_CFG,
170 pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
Marc Jones9ad593b2017-06-22 22:19:55 -0600171}
Marc Jones2d79f162017-05-22 21:35:16 -0600172
173/*************************************************
Marshall Dawsonbeb12882017-05-23 18:57:47 -0600174 * Dedicated mainboard function
Marc Jones2d79f162017-05-22 21:35:16 -0600175 *************************************************/
176static void kahlee_enable(device_t dev)
177{
178 printk(BIOS_INFO, "Mainboard "
179 CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
180
181 /* Initialize the PIRQ data structures for consumption */
182 pirq_setup();
Marc Jones0a15ed52017-06-22 22:22:20 -0600183
184 dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
Marc Jones2d79f162017-05-22 21:35:16 -0600185}
186
Marc Jones067031e2017-11-02 11:36:53 -0600187
188static void mainboard_final(void *chip_info)
189{
190 struct global_nvs_t *gnvs;
191
192 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
193
194 if (gnvs) {
195 gnvs->tmps = CTL_TDP_SENSOR_ID;
196 gnvs->tcrt = CRITICAL_TEMPERATURE;
197 gnvs->tpsv = PASSIVE_TEMPERATURE;
198 }
199}
200
Marc Jonesdf6b51b2017-11-29 20:07:46 -0700201int mainboard_get_xhci_oc_map(uint16_t *map)
202{
203 return variant_get_xhci_oc_map(map);
204}
205
206int mainboard_get_ehci_oc_map(uint16_t *map)
207{
208 return variant_get_ehci_oc_map(map);
209}
210
Marc Jones2d79f162017-05-22 21:35:16 -0600211struct chip_operations mainboard_ops = {
Marc Jones9ad593b2017-06-22 22:19:55 -0600212 .init = mainboard_init,
Marc Jones2d79f162017-05-22 21:35:16 -0600213 .enable_dev = kahlee_enable,
Marc Jones067031e2017-11-02 11:36:53 -0600214 .final = mainboard_final,
Marc Jones2d79f162017-05-22 21:35:16 -0600215};