blob: 283470bc275808a6089d1bbca14dead7caf179f8 [file] [log] [blame]
Felix Held0ffebac2021-02-05 22:26:00 +01001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
Raul E Rangelf2df29e2021-03-16 13:23:38 -06003#include <acpi/acpi_device.h>
Raul E Rangelf486fcc2021-03-16 20:29:06 -06004#include <acpi/acpigen.h>
5#include <acpi/acpigen_pci.h>
6#include <amdblocks/amd_pci_util.h>
7#include <assert.h>
Raul E Rangelf2df29e2021-03-16 13:23:38 -06008#include <console/console.h>
Felix Held0ffebac2021-02-05 22:26:00 +01009#include <device/device.h>
10#include <device/pci.h>
11#include <device/pci_ids.h>
Felix Held08105382021-02-16 18:46:01 +010012#include <device/pciexp.h>
Raul E Rangelf2df29e2021-03-16 13:23:38 -060013#include <soc/pci_devs.h>
14
15static const char *pcie_gpp_acpi_name(const struct device *dev)
16{
17 if (dev->path.type != DEVICE_PATH_PCI)
18 return NULL;
19
20 switch (dev->path.pci.devfn) {
21 case PCIE_GPP_1_0_DEVFN:
22 return "GP10";
23 case PCIE_GPP_1_1_DEVFN:
24 return "GP11";
25 case PCIE_GPP_1_2_DEVFN:
26 return "GP12";
27 case PCIE_GPP_2_0_DEVFN:
28 return "GP20";
29 case PCIE_GPP_2_1_DEVFN:
30 return "GP21";
31 case PCIE_GPP_2_2_DEVFN:
32 return "GP22";
33 case PCIE_GPP_2_3_DEVFN:
34 return "GP23";
35 case PCIE_GPP_2_4_DEVFN:
36 return "GP24";
37 case PCIE_GPP_2_5_DEVFN:
38 return "GP25";
39 case PCIE_GPP_2_6_DEVFN:
40 return "GP26";
41 case PCIE_ABC_A_DEVFN:
42 return "GPPA";
43 case PCIE_GPP_B_DEVFN:
44 return "GPPB";
45 case PCIE_GPP_C_DEVFN:
46 return "GPPC";
47 default:
48 printk(BIOS_ERR, "%s: Unhanded devfn 0x%x\n", __func__, dev->path.pci.devfn);
49 return NULL;
50 }
51}
Felix Held0ffebac2021-02-05 22:26:00 +010052
Raul E Rangelf486fcc2021-03-16 20:29:06 -060053static void acpi_device_write_gpp_pci_dev(const struct device *dev)
54{
55 const char *scope = acpi_device_scope(dev);
56 const char *name = acpi_device_name(dev);
57
58 assert(dev->path.type == DEVICE_PATH_PCI);
59 assert(name);
60 assert(scope);
61
62 acpigen_write_scope(scope);
63 acpigen_write_device(name);
64
65 acpigen_write_ADR_pci_device(dev);
66 acpigen_write_STA(acpi_device_status(dev));
67
Raul E Rangel506ee242021-05-07 12:30:49 -060068 acpigen_write_pci_GNB_PRT(dev);
Raul E Rangelf486fcc2021-03-16 20:29:06 -060069
70 acpigen_pop_len(); /* Device */
71 acpigen_pop_len(); /* Scope */
72}
73
Felix Held0ffebac2021-02-05 22:26:00 +010074static struct device_operations internal_pcie_gpp_ops = {
75 .read_resources = pci_bus_read_resources,
76 .set_resources = pci_dev_set_resources,
77 .enable_resources = pci_bus_enable_resources,
78 .scan_bus = pci_scan_bridge,
79 .reset_bus = pci_bus_reset,
Raul E Rangelf2df29e2021-03-16 13:23:38 -060080 .acpi_name = pcie_gpp_acpi_name,
Raul E Rangelf486fcc2021-03-16 20:29:06 -060081 .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev,
Felix Held0ffebac2021-02-05 22:26:00 +010082};
83
Felix Held0ffebac2021-02-05 22:26:00 +010084static const struct pci_driver internal_pcie_gpp_driver __pci_driver = {
85 .ops = &internal_pcie_gpp_ops,
86 .vendor = PCI_VENDOR_ID_AMD,
Felix Heldabeecec2021-02-16 18:42:15 +010087 .device = PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC,
Felix Held0ffebac2021-02-05 22:26:00 +010088};
Felix Held08105382021-02-16 18:46:01 +010089
90static struct device_operations external_pcie_gpp_ops = {
91 .read_resources = pci_bus_read_resources,
92 .set_resources = pci_dev_set_resources,
93 .enable_resources = pci_bus_enable_resources,
94 .scan_bus = pciexp_scan_bridge,
95 .reset_bus = pci_bus_reset,
Raul E Rangelf2df29e2021-03-16 13:23:38 -060096 .acpi_name = pcie_gpp_acpi_name,
Raul E Rangelf486fcc2021-03-16 20:29:06 -060097 .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev,
Felix Held08105382021-02-16 18:46:01 +010098};
99
100static const unsigned short external_pci_gpp_ids[] = {
101 PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1,
102 PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2,
103 0
104};
105
106static const struct pci_driver external_pcie_gpp_driver __pci_driver = {
107 .ops = &external_pcie_gpp_ops,
108 .vendor = PCI_VENDOR_ID_AMD,
109 .devices = external_pci_gpp_ids,
110};