Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <boot/tables.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <cpu/amd/mtrr.h> |
| 27 | #include <device/pci_def.h> |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 28 | #include "southbridge/amd/sb700/sb700.h" |
| 29 | #include "southbridge/amd/sb700/smbus.h" |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 30 | #include "chip.h" |
| 31 | |
| 32 | #define ADT7461_ADDRESS 0x4C |
| 33 | #define ARA_ADDRESS 0x0C /* Alert Response Address */ |
| 34 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 35 | #define ADT7461_read_byte(address) \ |
| 36 | do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) |
| 37 | #define ARA_read_byte(address) \ |
| 38 | do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) |
| 39 | #define ADT7461_write_byte(address, val) \ |
| 40 | do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) |
| 41 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 42 | void set_pcie_dereset(void); |
| 43 | void set_pcie_reset(void); |
| 44 | int is_dev3_present(void); |
| 45 | |
| 46 | void set_pcie_dereset() |
| 47 | { |
| 48 | u8 byte; |
| 49 | u16 word; |
| 50 | device_t sm_dev; |
| 51 | /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ |
| 52 | /* set 0 to bit2 :disable GPM8 as AZ_RST output */ |
| 53 | byte = pm_ioread(0x8d); |
| 54 | byte &= ~((1 << 1) | (1 << 2)); |
| 55 | pm_iowrite(0x8d, byte); |
| 56 | |
| 57 | /* set the GPM8 and GPM9 output enable and the value to 1 */ |
| 58 | byte = pm_ioread(0x94); |
| 59 | byte &= ~((1 << 2) | (1 << 3)); |
| 60 | byte |= ((1 << 0) | (1 << 1)); |
| 61 | pm_iowrite(0x94, byte); |
| 62 | |
| 63 | /* set the GPIO65 output enable and the value is 1 */ |
| 64 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 65 | word = pci_read_config16(sm_dev, 0x7e); |
| 66 | word |= (1 << 0); |
| 67 | word &= ~(1 << 4); |
| 68 | pci_write_config16(sm_dev, 0x7e, word); |
| 69 | } |
| 70 | |
| 71 | void set_pcie_reset() |
| 72 | { |
| 73 | u8 byte; |
| 74 | u16 word; |
| 75 | device_t sm_dev; |
| 76 | |
| 77 | /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ |
| 78 | /* set 0 to bit2 :disable GPM8 as AZ_RST output */ |
| 79 | byte = pm_ioread(0x8d); |
| 80 | byte &= ~((1 << 1) | (1 << 2)); |
| 81 | pm_iowrite(0x8d, byte); |
| 82 | |
| 83 | /* set the GPM8 and GPM9 output enable and the value to 0 */ |
| 84 | byte = pm_ioread(0x94); |
| 85 | byte &= ~((1 << 2) | (1 << 3)); |
| 86 | byte &= ~((1 << 0) | (1 << 1)); |
| 87 | pm_iowrite(0x94, byte); |
| 88 | |
| 89 | /* set the GPIO65 output enable and the value is 0 */ |
| 90 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 91 | word = pci_read_config16(sm_dev, 0x7e); |
| 92 | word &= ~(1 << 0); |
| 93 | word &= ~(1 << 4); |
| 94 | pci_write_config16(sm_dev, 0x7e, word); |
| 95 | } |
| 96 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 97 | /* |
| 98 | * justify the dev3 is exist or not |
| 99 | */ |
| 100 | int is_dev3_present(void) |
| 101 | { |
| 102 | u16 word; |
| 103 | device_t sm_dev; |
| 104 | |
| 105 | /* access the smbus extended register */ |
| 106 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 107 | |
| 108 | /* put the GPIO68 output to tristate */ |
| 109 | word = pci_read_config16(sm_dev, 0x7e); |
| 110 | word |= 1 << 6; |
| 111 | pci_write_config16(sm_dev, 0x7e,word); |
| 112 | |
| 113 | /* read the GPIO68 input status */ |
| 114 | word = pci_read_config16(sm_dev, 0x7e); |
| 115 | |
| 116 | if(word & (1 << 10)){ |
| 117 | /*not exist*/ |
| 118 | return 0; |
| 119 | }else{ |
| 120 | /*exist*/ |
| 121 | return 1; |
| 122 | } |
| 123 | } |
| 124 | |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 125 | /* |
| 126 | * set gpio40 gfx |
| 127 | */ |
| 128 | static void set_gpio40_gfx(void) |
| 129 | { |
| 130 | u8 byte; |
| 131 | // u16 word; |
| 132 | u32 dword; |
| 133 | device_t sm_dev; |
| 134 | /* disable the GPIO40 as CLKREQ2# function */ |
| 135 | byte = pm_ioread(0xd3); |
| 136 | byte &= ~(1 << 7); |
| 137 | pm_iowrite(0xd3, byte); |
| 138 | |
| 139 | /* disable the GPIO40 as CLKREQ3# function */ |
| 140 | byte = pm_ioread(0xd4); |
| 141 | byte &= ~(1 << 0); |
| 142 | pm_iowrite(0xd4, byte); |
| 143 | |
| 144 | /* enable pull up for GPIO68 */ |
| 145 | byte = pm2_ioread(0xf1); |
| 146 | byte &= ~(1 << 4); |
| 147 | pm2_iowrite(0xf1, byte); |
| 148 | |
| 149 | /* access the smbus extended register */ |
| 150 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 151 | |
| 152 | /*if the dev3 is present, set the gfx to 2x8 lanes*/ |
| 153 | /*otherwise set the gfx to 1x16 lanes*/ |
| 154 | if(is_dev3_present()){ |
| 155 | |
| 156 | printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); |
| 157 | /* when the gpio40 is configured as GPIO, this will enable the output */ |
| 158 | pci_write_config32(sm_dev, 0xf8, 0x4); |
| 159 | dword = pci_read_config32(sm_dev, 0xfc); |
| 160 | dword &= ~(1 << 10); |
| 161 | |
| 162 | /* When the gpio40 is configured as GPIO, this will represent the output value*/ |
| 163 | /* 1 :enable two x8 , 0 : master slot enable only */ |
| 164 | dword |= (1 << 26); |
| 165 | pci_write_config32(sm_dev, 0xfc, dword); |
| 166 | |
| 167 | }else{ |
| 168 | printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); |
| 169 | /* when the gpio40 is configured as GPIO, this will enable the output */ |
| 170 | pci_write_config32(sm_dev, 0xf8, 0x4); |
| 171 | dword = pci_read_config32(sm_dev, 0xfc); |
| 172 | dword &= ~(1 << 10); |
| 173 | |
| 174 | /* When the gpio40 is configured as GPIO, this will represent the output value*/ |
| 175 | /* 1 :enable two x8 , 0 : master slot enable only */ |
| 176 | dword &= ~(1 << 26); |
| 177 | pci_write_config32(sm_dev, 0xfc, dword); |
| 178 | } |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * set thermal config |
| 183 | */ |
| 184 | static void set_thermal_config(void) |
| 185 | { |
| 186 | u8 byte; |
| 187 | u16 word; |
| 188 | device_t sm_dev; |
| 189 | |
| 190 | /* set ADT 7461 */ |
| 191 | ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ |
| 192 | ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ |
| 193 | ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ |
| 194 | ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ |
| 195 | |
| 196 | ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ |
| 197 | ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ |
| 198 | |
| 199 | byte = ADT7461_read_byte(0x02); /* read status register to clear it */ |
| 200 | ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ |
| 201 | printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); |
| 202 | |
| 203 | /* sb700 settings for thermal config */ |
| 204 | /* set SB700 GPIO 64 to GPIO with pull-up */ |
| 205 | byte = pm2_ioread(0x42); |
| 206 | byte &= 0x3f; |
| 207 | pm2_iowrite(0x42, byte); |
| 208 | |
| 209 | /* set GPIO 64 to input */ |
| 210 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 211 | word = pci_read_config16(sm_dev, 0x56); |
| 212 | word |= 1 << 7; |
| 213 | pci_write_config16(sm_dev, 0x56, word); |
| 214 | |
| 215 | /* set GPIO 64 internal pull-up */ |
| 216 | byte = pm2_ioread(0xf0); |
| 217 | byte &= 0xee; |
| 218 | pm2_iowrite(0xf0, byte); |
| 219 | |
| 220 | /* set Talert to be active low */ |
| 221 | byte = pm_ioread(0x67); |
| 222 | byte &= ~(1 << 5); |
| 223 | pm_iowrite(0x67, byte); |
| 224 | |
| 225 | /* set Talert to generate ACPI event */ |
| 226 | byte = pm_ioread(0x3c); |
| 227 | byte &= 0xf3; |
| 228 | pm_iowrite(0x3c, byte); |
| 229 | |
| 230 | /* THERMTRIP pin */ |
| 231 | /* byte = pm_ioread(0x68); |
| 232 | * byte |= 1 << 3; |
| 233 | * pm_iowrite(0x68, byte); |
| 234 | * |
| 235 | * byte = pm_ioread(0x55); |
| 236 | * byte |= 1 << 0; |
| 237 | * pm_iowrite(0x55, byte); |
| 238 | * |
| 239 | * byte = pm_ioread(0x67); |
| 240 | * byte &= ~( 1 << 6); |
| 241 | * pm_iowrite(0x67, byte); |
| 242 | */ |
| 243 | } |
| 244 | |
| 245 | /************************************************* |
| 246 | * enable the dedicated function in ma785gmt board. |
| 247 | * This function called early than rs780_enable. |
| 248 | *************************************************/ |
| 249 | static void ma785gmt_enable(device_t dev) |
| 250 | { |
Alec Ari | bc081cd | 2011-08-21 22:09:53 -0500 | [diff] [blame] | 251 | printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 252 | |
Kyösti Mälkki | 231f261 | 2012-07-11 08:02:57 +0300 | [diff] [blame] | 253 | setup_uma_memory(); |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 254 | |
| 255 | set_pcie_dereset(); |
| 256 | /* get_ide_dma66(); */ |
| 257 | set_thermal_config(); |
| 258 | set_gpio40_gfx(); |
| 259 | } |
| 260 | |
| 261 | int add_mainboard_resources(struct lb_memory *mem) |
| 262 | { |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | struct chip_operations mainboard_ops = { |
Alec Ari | bc081cd | 2011-08-21 22:09:53 -0500 | [diff] [blame] | 267 | CHIP_NAME("GIGABYTE MA785GMT-UD2H Mainboard") |
Wang Qing Pei | 3f90125 | 2010-08-17 11:08:31 +0000 | [diff] [blame] | 268 | .enable_dev = ma785gmt_enable, |
| 269 | }; |