Angel Pons | 230e4f9d | 2020-04-05 15:47:14 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <stdint.h> |
Lee Leahy | d76d60b | 2016-03-03 15:30:48 -0800 | [diff] [blame] | 7 | #include <fsp/util.h> |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 8 | #include <soc/pci_devs.h> |
| 9 | #include <soc/pm.h> |
| 10 | |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 11 | /// |
| 12 | /// MRC Flags bits |
| 13 | /// |
| 14 | #define MRC_FLAG_ECC_EN BIT0 |
| 15 | #define MRC_FLAG_SCRAMBLE_EN BIT1 |
| 16 | #define MRC_FLAG_MEMTEST_EN BIT2 |
| 17 | |
| 18 | /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ |
| 19 | #define MRC_FLAG_TOP_TREE_EN BIT3 |
| 20 | |
| 21 | /* If set ODR signal is asserted to DRAM devices on writes */ |
| 22 | #define MRC_FLAG_WR_ODT_EN BIT4 |
| 23 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 24 | struct soc_intel_quark_config { |
Lee Leahy | d76d60b | 2016-03-03 15:30:48 -0800 | [diff] [blame] | 25 | /* |
| 26 | * MemoryInit: |
| 27 | * |
| 28 | * The following fields come from FspUpdVpd.h and are defined as PCDs |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 29 | * for the FSP binary. Data for these fields comes from the board's |
Lee Leahy | d76d60b | 2016-03-03 15:30:48 -0800 | [diff] [blame] | 30 | * devicetree.cb file which gets processed into static.c and then |
| 31 | * built into the coreboot image. The fields below contain retain |
| 32 | * the FSP PCD field name. |
| 33 | */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 34 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 35 | uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 36 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 37 | uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */ |
| 38 | uint32_t tRAS; /* ACT to PRE command period in picoseconds */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 39 | |
| 40 | /* Delay from start of internal write transaction to internal read |
| 41 | * command in picoseconds |
| 42 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 43 | uint32_t tWTR; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 44 | |
| 45 | /* ACT to ACT command period (JESD79 specific to page size 1K/2K) in |
| 46 | * picoseconds |
| 47 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 48 | uint32_t tRRD; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 49 | |
| 50 | /* Four activate window (JESD79 specific to page size 1K/2K) in |
| 51 | * picoseconds |
| 52 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 53 | uint32_t tFAW; |
| 54 | uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 55 | |
| 56 | /* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU |
| 57 | * support 1066 memory |
| 58 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 59 | uint8_t DramSpeed; |
| 60 | uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 61 | |
| 62 | /* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 63 | uint8_t RankMask; |
| 64 | uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ |
| 65 | uint8_t ChanWidth; /* 1=x16, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 66 | |
| 67 | /* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 68 | uint8_t AddrMode; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 69 | |
| 70 | /* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 71 | uint8_t SrInt; |
| 72 | uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 73 | |
| 74 | /* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver |
| 75 | * impedance control. |
| 76 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 77 | uint8_t DramRonVal; |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame] | 78 | uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RSVD */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 79 | uint8_t DramRttWrVal; /* 0=off others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 80 | |
| 81 | /* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 82 | uint8_t SocRdOdtVal; |
| 83 | uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ |
| 84 | uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 85 | |
| 86 | /* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 87 | uint8_t DramDensity; |
| 88 | uint8_t tCL; /* DRAM CAS Latency in clocks */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 89 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 90 | /* ECC scrub interval in milliseconds 1..255 (0 works as feature |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 91 | * disable) |
| 92 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 93 | uint8_t EccScrubInterval; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 94 | |
| 95 | /* Number of 32B blocks read for ECC scrub 2..16 */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 96 | uint8_t EccScrubBlkSize; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 97 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 98 | uint8_t SmmTsegSize; /* SMM size in MiB */ |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 99 | }; |
| 100 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 101 | #endif |