Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame^] | 6 | * Copyright (C) 2015-2017 Intel Corporation. |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #ifndef _SOC_CHIP_H_ |
| 19 | #define _SOC_CHIP_H_ |
| 20 | |
| 21 | #include <stdint.h> |
Lee Leahy | d76d60b | 2016-03-03 15:30:48 -0800 | [diff] [blame] | 22 | #include <fsp/util.h> |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/pm.h> |
| 25 | |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 26 | /// |
| 27 | /// MRC Flags bits |
| 28 | /// |
| 29 | #define MRC_FLAG_ECC_EN BIT0 |
| 30 | #define MRC_FLAG_SCRAMBLE_EN BIT1 |
| 31 | #define MRC_FLAG_MEMTEST_EN BIT2 |
| 32 | |
| 33 | /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ |
| 34 | #define MRC_FLAG_TOP_TREE_EN BIT3 |
| 35 | |
| 36 | /* If set ODR signal is asserted to DRAM devices on writes */ |
| 37 | #define MRC_FLAG_WR_ODT_EN BIT4 |
| 38 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 39 | struct soc_intel_quark_config { |
Lee Leahy | d76d60b | 2016-03-03 15:30:48 -0800 | [diff] [blame] | 40 | /* |
| 41 | * MemoryInit: |
| 42 | * |
| 43 | * The following fields come from FspUpdVpd.h and are defined as PCDs |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame^] | 44 | * for the FSP binary. Data for these fields comes from the board's |
Lee Leahy | d76d60b | 2016-03-03 15:30:48 -0800 | [diff] [blame] | 45 | * devicetree.cb file which gets processed into static.c and then |
| 46 | * built into the coreboot image. The fields below contain retain |
| 47 | * the FSP PCD field name. |
| 48 | */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 49 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 50 | uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 51 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 52 | uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */ |
| 53 | uint32_t tRAS; /* ACT to PRE command period in picoseconds */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 54 | |
| 55 | /* Delay from start of internal write transaction to internal read |
| 56 | * command in picoseconds |
| 57 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 58 | uint32_t tWTR; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 59 | |
| 60 | /* ACT to ACT command period (JESD79 specific to page size 1K/2K) in |
| 61 | * picoseconds |
| 62 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 63 | uint32_t tRRD; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 64 | |
| 65 | /* Four activate window (JESD79 specific to page size 1K/2K) in |
| 66 | * picoseconds |
| 67 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 68 | uint32_t tFAW; |
| 69 | uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 70 | |
| 71 | /* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU |
| 72 | * support 1066 memory |
| 73 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 74 | uint8_t DramSpeed; |
| 75 | uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 76 | |
| 77 | /* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 78 | uint8_t RankMask; |
| 79 | uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ |
| 80 | uint8_t ChanWidth; /* 1=x16, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 81 | |
| 82 | /* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 83 | uint8_t AddrMode; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 84 | |
| 85 | /* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 86 | uint8_t SrInt; |
| 87 | uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 88 | |
| 89 | /* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver |
| 90 | * impedance control. |
| 91 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 92 | uint8_t DramRonVal; |
Lee Leahy | 94b971a | 2017-03-06 08:59:23 -0800 | [diff] [blame^] | 93 | uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RSVD */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 94 | uint8_t DramRttWrVal; /* 0=off others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 95 | |
| 96 | /* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 97 | uint8_t SocRdOdtVal; |
| 98 | uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ |
| 99 | uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 100 | |
| 101 | /* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 102 | uint8_t DramDensity; |
| 103 | uint8_t tCL; /* DRAM CAS Latency in clocks */ |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 104 | |
| 105 | /* ECC scrub interval in miliseconds 1..255 (0 works as feature |
| 106 | * disable) |
| 107 | */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 108 | uint8_t EccScrubInterval; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 109 | |
| 110 | /* Number of 32B blocks read for ECC scrub 2..16 */ |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 111 | uint8_t EccScrubBlkSize; |
Lee Leahy | dc54270 | 2016-06-18 18:52:43 -0700 | [diff] [blame] | 112 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 113 | uint8_t SmmTsegSize; /* SMM size in MiB */ |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 114 | }; |
| 115 | |
| 116 | extern struct chip_operations soc_ops; |
| 117 | |
| 118 | #endif |