Angel Pons | 230e4f9d | 2020-04-05 15:47:14 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 2 | |
Lee Leahy | 14d0926 | 2016-07-21 09:17:10 -0700 | [diff] [blame] | 3 | #include <assert.h> |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 4 | #include <device/device.h> |
Lee Leahy | 535333d | 2016-02-14 15:10:35 -0800 | [diff] [blame] | 5 | #include <soc/ramstage.h> |
Lee Leahy | 63e3dff | 2016-04-30 08:48:52 -0700 | [diff] [blame] | 6 | #include <soc/reg_access.h> |
| 7 | |
| 8 | /* Cat Trip Clear value must be less than Cat Trip Set value */ |
| 9 | #define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105 |
| 10 | #define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65 |
| 11 | |
| 12 | static const struct reg_script thermal_init_script[] = { |
| 13 | |
| 14 | /* Setup RMU Thermal sensor registers for Ratiometric mode. */ |
| 15 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG, |
| 16 | ~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK |
| 17 | | B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK |
| 18 | | B_TSCGF1_CONFIG_ISNSINTERNALVREFEN |
| 19 | | B_TSCGF1_CONFIG_IBGEN |
| 20 | | B_TSCGF1_CONFIG_IBGCHOPEN), |
| 21 | ((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE |
| 22 | << B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP) |
| 23 | | (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE |
| 24 | << B_TSCGF1_CONFIG_ISNSCHOPSEL_BP) |
| 25 | | (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE |
| 26 | << B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP) |
| 27 | | (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE |
| 28 | << B_TSCGF1_CONFIG_IBGEN_BP) |
| 29 | | (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE |
| 30 | << B_TSCGF1_CONFIG_IBGCHOPEN_BP))), |
| 31 | |
| 32 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2, |
| 33 | ~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK |
| 34 | | B_TSCGF2_CONFIG2_ISPARECTRL_MASK |
| 35 | | B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK), |
| 36 | ((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE |
| 37 | << B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP) |
| 38 | | (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE |
| 39 | << B_TSCGF2_CONFIG2_ISPARECTRL_BP) |
| 40 | | (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE |
| 41 | << B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))), |
| 42 | |
| 43 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG, |
| 44 | ~(B_TSCGF2_CONFIG_IDSCONTROL_MASK |
| 45 | | B_TSCGF2_CONFIG_IDSTIMING_MASK), |
| 46 | ((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE |
| 47 | << B_TSCGF2_CONFIG_IDSCONTROL_BP) |
| 48 | | (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE |
| 49 | << B_TSCGF2_CONFIG_IDSTIMING_BP))), |
| 50 | |
| 51 | REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, |
| 52 | ~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK, |
| 53 | V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE |
| 54 | << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP), |
| 55 | |
| 56 | /* Enable RMU Thermal sensor with a Catastrophic Trip point. */ |
| 57 | |
| 58 | /* Set up Catastrophic Trip point. |
| 59 | * |
| 60 | * Trip Register fields are 8-bit temperature values of granularity 1 |
| 61 | * degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds |
| 62 | * to 205 degrees C. |
| 63 | * |
| 64 | * Add 50 to Celsius values to get values for register fields. |
| 65 | */ |
| 66 | REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP, |
| 67 | ~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK), |
| 68 | (((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50) |
| 69 | << TS_CAT_TRIP_SET_THOLD_BP) |
| 70 | | ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50) |
| 71 | << TS_CAT_TRIP_CLEAR_THOLD_BP))), |
| 72 | |
| 73 | /* To enable the TS do the following: |
| 74 | * 1) Take the TS out of reset by setting itsrst to 0x0. |
| 75 | * 2) Enable the TS using RMU Thermal sensor mode register. |
| 76 | */ |
| 77 | REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG, |
| 78 | ~B_TSCGF3_CONFIG_ITSRST), |
| 79 | REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE), |
| 80 | |
| 81 | /* Lock all RMU Thermal sensor control & trip point registers. */ |
| 82 | REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE |
| 83 | | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE), |
| 84 | REG_SCRIPT_END |
| 85 | }; |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 86 | |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 87 | static void chip_init(void *chip_info) |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 88 | { |
Lee Leahy | 63e3dff | 2016-04-30 08:48:52 -0700 | [diff] [blame] | 89 | /* Validate the temperature settings */ |
| 90 | ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); |
| 91 | ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS |
| 92 | > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); |
| 93 | |
| 94 | /* Set the temperature settings */ |
| 95 | reg_script_run(thermal_init_script); |
| 96 | |
| 97 | /* Verify that the thermal configuration is locked */ |
| 98 | ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) |
| 99 | & (TS_LOCK_THRM_CTRL_REGS_ENABLE |
| 100 | | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) |
| 101 | == (TS_LOCK_THRM_CTRL_REGS_ENABLE |
| 102 | | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); |
| 103 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 104 | /* Perform silicon specific init. */ |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 105 | fsp_silicon_init(); |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 106 | } |
| 107 | |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 108 | static struct device_operations pci_domain_ops = { |
| 109 | .read_resources = pci_domain_read_resources, |
| 110 | .set_resources = pci_domain_set_resources, |
| 111 | .scan_bus = pci_domain_scan_bus, |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 112 | }; |
| 113 | |
Elyes HAOUAS | 696545d | 2018-05-25 13:11:37 +0200 | [diff] [blame] | 114 | static void chip_enable_dev(struct device *dev) |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 115 | { |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 116 | |
| 117 | /* Set the operations if it is a special bus type */ |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 118 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 119 | dev->ops = &pci_domain_ops; |
| 120 | } |
| 121 | |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 122 | struct chip_operations soc_intel_quark_ops = { |
| 123 | CHIP_NAME("Intel Quark") |
Lee Leahy | b457649 | 2016-02-14 14:33:45 -0800 | [diff] [blame] | 124 | .init = &chip_init, |
| 125 | .enable_dev = chip_enable_dev, |
Lee Leahy | d4edacb | 2016-02-08 07:12:30 -0800 | [diff] [blame] | 126 | }; |