blob: d1767523dde17ed357c2684199186be0927c5b9a [file] [log] [blame]
Nico Huber1fa72d5f2020-09-24 23:33:34 +02001config SOC_EXAMPLE_MIN86
2 bool
3 help
4 This example SoC code along with the example/min86 mainboard
5 should serve as a minimal example how a buildable x86 SoC code
6 base can look like.
7
8 This can serve, for instance, as a basis to add new SoCs to
9 coreboot. Starting with a buildable commit should help with
10 the review of the actual code, and also avoid any regressions
11 when common coreboot code changes.
12
13if SOC_EXAMPLE_MIN86
14
15config SOC_SPECIFIC_OPTIONS
16 def_bool y
Angel Pons8e035e32021-06-22 12:58:20 +020017 select ARCH_X86
Nico Huber1fa72d5f2020-09-24 23:33:34 +020018 select NO_MONOTONIC_TIMER
Shelley Chen4e9bb332021-10-20 15:43:45 -070019 select NO_ECAM_MMCONF_SUPPORT
Nico Huber1fa72d5f2020-09-24 23:33:34 +020020 select UNKNOWN_TSC_RATE
21
Nico Huber1fa72d5f2020-09-24 23:33:34 +020022config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
23 default 0x100
24
25endif