| Nico Huber | 1fa72d5f | 2020-09-24 23:33:34 +0200 | [diff] [blame] | 1 | config SOC_EXAMPLE_MIN86 |
| 2 | bool |
| 3 | help |
| 4 | This example SoC code along with the example/min86 mainboard |
| 5 | should serve as a minimal example how a buildable x86 SoC code |
| 6 | base can look like. |
| 7 | |
| 8 | This can serve, for instance, as a basis to add new SoCs to |
| 9 | coreboot. Starting with a buildable commit should help with |
| 10 | the review of the actual code, and also avoid any regressions |
| 11 | when common coreboot code changes. |
| 12 | |
| 13 | if SOC_EXAMPLE_MIN86 |
| 14 | |
| 15 | config SOC_SPECIFIC_OPTIONS |
| 16 | def_bool y |
| 17 | select ARCH_ALL_STAGES_X86_32 |
| Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame^] | 18 | select ARCH_X86 |
| Nico Huber | 1fa72d5f | 2020-09-24 23:33:34 +0200 | [diff] [blame] | 19 | select NO_MONOTONIC_TIMER |
| 20 | select NO_MMCONF_SUPPORT |
| 21 | select UNKNOWN_TSC_RATE |
| 22 | |
| 23 | config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld |
| 24 | default 0x100 |
| 25 | |
| 26 | endif |