Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Marshall Dawson | a5f225f | 2017-08-18 10:07:07 -0600 | [diff] [blame] | 4 | #include <assert.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 5 | #include <console/console.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 7 | #include <cpu/amd/msr.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 8 | #include <cpu/x86/mtrr.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 9 | #include <smp/node.h> |
| 10 | #include <bootblock_common.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 11 | #include <amdblocks/agesawrapper.h> |
| 12 | #include <amdblocks/agesawrapper_call.h> |
Michał Żygowski | 200d213 | 2019-12-06 12:07:52 +0100 | [diff] [blame] | 13 | #include <amdblocks/amd_pci_mmconf.h> |
Michał Żygowski | 5a66202 | 2019-12-02 17:02:00 +0100 | [diff] [blame] | 14 | #include <amdblocks/biosram.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 15 | #include <amdblocks/i2c.h> |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 16 | #include <soc/pci_devs.h> |
Marshall Dawson | d85c4af | 2018-03-28 19:48:42 -0600 | [diff] [blame] | 17 | #include <soc/cpu.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 18 | #include <soc/southbridge.h> |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 19 | #include <timestamp.h> |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 20 | #include <halt.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 21 | |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 22 | #include "chip.h" |
| 23 | |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 24 | #if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 |
| 25 | #error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" |
| 26 | #endif |
| 27 | #if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 |
| 28 | #error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" |
| 29 | #endif |
| 30 | |
Felix Held | 916cd50 | 2021-08-04 17:22:36 +0200 | [diff] [blame] | 31 | /* Table to switch SCL pins to outputs to initially reset the I2C peripherals */ |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 32 | static const struct soc_i2c_scl_pin i2c_scl_pins[] = { |
Felix Held | 7bbde76 | 2021-09-08 00:37:30 +0200 | [diff] [blame] | 33 | I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL), |
| 34 | I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL), |
| 35 | I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL), |
| 36 | I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL), |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 37 | }; |
| 38 | |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 39 | /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 40 | static void amd_initmmio(void) |
| 41 | { |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 42 | msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 43 | int mtrr; |
| 44 | |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 45 | /* |
| 46 | * todo: AGESA currently writes variable MTRRs. Once that is |
| 47 | * corrected, un-hardcode this MTRR. |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 48 | * |
| 49 | * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs |
| 50 | * where all cores execute the path. Both cores within a compute |
| 51 | * unit share MTRRs. Programming core0 has the appearance of |
| 52 | * modifying core1 too. Using the pair again will create |
| 53 | * duplicate copies. |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 54 | */ |
Marshall Dawson | d85c4af | 2018-03-28 19:48:42 -0600 | [diff] [blame] | 55 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 56 | set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 57 | |
| 58 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; |
| 59 | set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, |
| 60 | CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); |
| 61 | |
| 62 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; |
| 63 | set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, |
| 64 | CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 65 | } |
| 66 | |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 67 | static void reset_i2c_peripherals(void) |
| 68 | { |
| 69 | const struct soc_amd_stoneyridge_config *cfg = config_of_soc(); |
| 70 | struct soc_i2c_peripheral_reset_info reset_info; |
| 71 | |
| 72 | reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK; |
| 73 | reset_info.i2c_scl = i2c_scl_pins; |
| 74 | reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins); |
| 75 | sb_reset_i2c_peripherals(&reset_info); |
| 76 | } |
| 77 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 78 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 79 | { |
Michał Żygowski | 200d213 | 2019-12-06 12:07:52 +0100 | [diff] [blame] | 80 | enable_pci_mmconf(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 81 | amd_initmmio(); |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 82 | /* |
| 83 | * Call lib/bootblock.c main with BSP, shortcut for APs |
| 84 | */ |
| 85 | if (!boot_cpu()) { |
| 86 | void (*ap_romstage_entry)(void) = |
| 87 | (void (*)(void))get_ap_entry_ptr(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 88 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 89 | ap_romstage_entry(); /* execution does not return */ |
| 90 | halt(); |
| 91 | } |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 92 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 93 | /* TSC cannot be relied upon. Override the TSC value passed in. */ |
Kyösti Mälkki | 101ef0b | 2019-08-18 06:58:42 +0300 | [diff] [blame] | 94 | bootblock_main_with_basetime(timestamp_get()); |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | void bootblock_soc_early_init(void) |
| 98 | { |
Richard Spiegel | 5401aa2 | 2018-09-11 11:36:38 -0700 | [diff] [blame] | 99 | /* |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 100 | * This call (sb_reset_i2c_peripherals) was originally early at |
Richard Spiegel | 5401aa2 | 2018-09-11 11:36:38 -0700 | [diff] [blame] | 101 | * bootblock_c_entry, but had to be moved here. There was an |
| 102 | * unexplained delay in the middle of the i2c transaction when |
| 103 | * we had it in bootblock_c_entry. Moving it to this point |
| 104 | * (or adding delays) fixes the issue. It seems like the processor |
| 105 | * just pauses but we don't know why. |
| 106 | */ |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 107 | reset_i2c_peripherals(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 108 | bootblock_fch_early_init(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 109 | post_code(0x90); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | void bootblock_soc_init(void) |
| 113 | { |
Felix Held | 91ef925 | 2021-01-12 23:44:05 +0100 | [diff] [blame] | 114 | if (CONFIG(AMD_SOC_CONSOLE_UART)) |
Marshall Dawson | a5f225f | 2017-08-18 10:07:07 -0600 | [diff] [blame] | 115 | assert(CONFIG_UART_FOR_CONSOLE >= 0 |
| 116 | && CONFIG_UART_FOR_CONSOLE <= 1); |
| 117 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 118 | u32 val = cpuid_eax(1); |
| 119 | printk(BIOS_DEBUG, "Family_Model: %08x\n", val); |
| 120 | |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 121 | bootblock_fch_init(); |
| 122 | |
Aaron Durbin | de3e84c | 2018-01-29 17:44:58 -0700 | [diff] [blame] | 123 | /* Initialize any early i2c buses. */ |
| 124 | i2c_soc_early_init(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 125 | } |