Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 4 | #include <symbols.h> |
Felix Held | 8485637 | 2020-12-10 00:06:12 +0100 | [diff] [blame] | 5 | #include <amdblocks/cpu.h> |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 6 | #include <amdblocks/reset.h> |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 7 | #include <bootblock_common.h> |
| 8 | #include <console/console.h> |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 9 | #include <cpu/x86/cache.h> |
| 10 | #include <cpu/x86/msr.h> |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 11 | #include <cpu/x86/mtrr.h> |
| 12 | #include <cpu/amd/mtrr.h> |
Kangheui Won | 1464b0e | 2020-09-17 17:04:12 +1000 | [diff] [blame] | 13 | #include <cpu/x86/tsc.h> |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 14 | #include <pc80/mc146818rtc.h> |
| 15 | #include <soc/psp_transfer.h> |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 16 | #include <soc/southbridge.h> |
| 17 | #include <soc/i2c.h> |
| 18 | #include <amdblocks/amd_pci_mmconf.h> |
| 19 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 20 | /* PSP performs the memory training and setting up DRAM map prior to x86 cores |
| 21 | being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, |
| 22 | route lower memory addresses covered by fixed MTRRs to DRAM except for |
| 23 | 0xa0000-0xc0000 . */ |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 24 | static void set_caching(void) |
| 25 | { |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 26 | msr_t top_mem; |
| 27 | msr_t sys_cfg; |
| 28 | msr_t mtrr_def_type; |
| 29 | msr_t fixed_mtrr_ram; |
| 30 | msr_t fixed_mtrr_mmio; |
| 31 | struct var_mtrr_context mtrr_ctx; |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 32 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 33 | var_mtrr_context_init(&mtrr_ctx, NULL); |
| 34 | top_mem = rdmsr(TOP_MEM); |
| 35 | /* Enable RdDram and WrDram attributes in fixed MTRRs. */ |
| 36 | sys_cfg = rdmsr(SYSCFG_MSR); |
| 37 | sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 38 | |
| 39 | /* Fixed MTRR constants. */ |
| 40 | fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = |
| 41 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | |
| 42 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | |
| 43 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | |
| 44 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); |
| 45 | fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = |
| 46 | ((MTRR_TYPE_UNCACHEABLE) << 0) | |
| 47 | ((MTRR_TYPE_UNCACHEABLE) << 8) | |
| 48 | ((MTRR_TYPE_UNCACHEABLE) << 16) | |
| 49 | ((MTRR_TYPE_UNCACHEABLE) << 24); |
| 50 | |
| 51 | /* Prep default MTRR type. */ |
| 52 | mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); |
| 53 | mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; |
| 54 | mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; |
| 55 | mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; |
| 56 | |
| 57 | disable_cache(); |
| 58 | |
| 59 | wrmsr(SYSCFG_MSR, sys_cfg); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 60 | |
| 61 | clear_all_var_mtrr(); |
| 62 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 63 | var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); |
| 64 | var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 65 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 66 | /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ |
| 67 | wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); |
| 68 | wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); |
| 69 | wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); |
| 70 | wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); |
| 71 | wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); |
| 72 | wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); |
| 73 | wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); |
| 74 | wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); |
| 75 | wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); |
| 76 | wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); |
| 77 | wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 78 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 79 | wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); |
| 80 | |
| 81 | /* Enable Fixed and Variable MTRRs. */ |
| 82 | sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; |
| 83 | sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; |
| 84 | /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once |
| 85 | MP init happens in coreboot proper it can be knocked down. */ |
| 86 | wrmsr(SYSCFG_MSR, sys_cfg); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 87 | |
| 88 | enable_cache(); |
| 89 | } |
| 90 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 91 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
| 92 | { |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 93 | set_caching(); |
Raul E Rangel | ec26428 | 2020-06-04 16:42:50 -0600 | [diff] [blame] | 94 | write_resume_eip(); |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 95 | enable_pci_mmconf(); |
| 96 | |
Kangheui Won | 1464b0e | 2020-09-17 17:04:12 +1000 | [diff] [blame] | 97 | /* |
| 98 | * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz |
| 99 | * when we use micro-seconds granularity for Zork |
| 100 | */ |
| 101 | base_timestamp /= tsc_freq_mhz(); |
| 102 | |
| 103 | if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) |
| 104 | boot_with_psp_timestamp(base_timestamp); |
| 105 | |
| 106 | /* |
| 107 | * if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or |
| 108 | * previous step did nothing, proceed with normal bootblock main. |
| 109 | */ |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 110 | bootblock_main_with_basetime(base_timestamp); |
| 111 | } |
| 112 | |
| 113 | void bootblock_soc_early_init(void) |
| 114 | { |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 115 | fch_pre_init(); |
| 116 | } |
| 117 | |
| 118 | void bootblock_soc_init(void) |
| 119 | { |
| 120 | u32 val = cpuid_eax(1); |
| 121 | printk(BIOS_DEBUG, "Family_Model: %08x\n", val); |
| 122 | |
Martin Roth | 4b34193 | 2020-10-06 15:29:28 -0600 | [diff] [blame] | 123 | if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { |
| 124 | verify_psp_transfer_buf(); |
Martin Roth | 0f3ef70 | 2020-10-06 18:11:12 -0600 | [diff] [blame] | 125 | show_psp_transfer_info(); |
Martin Roth | 95d05e4 | 2020-06-24 19:42:44 -0600 | [diff] [blame] | 126 | } |
Martin Roth | 95d05e4 | 2020-06-24 19:42:44 -0600 | [diff] [blame] | 127 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 128 | fch_early_init(); |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 129 | } |