Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| 3 | |
| 4 | #include <stdint.h> |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame^] | 5 | #include <symbols.h> |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 6 | #include <bootblock_common.h> |
| 7 | #include <console/console.h> |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame^] | 8 | #include <cpu/x86/cache.h> |
| 9 | #include <cpu/x86/msr.h> |
| 10 | #include <cpu/amd/msr.h> |
| 11 | #include <cpu/x86/mtrr.h> |
| 12 | #include <cpu/amd/mtrr.h> |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 13 | #include <soc/southbridge.h> |
| 14 | #include <soc/i2c.h> |
| 15 | #include <amdblocks/amd_pci_mmconf.h> |
| 16 | |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame^] | 17 | static void set_caching(void) |
| 18 | { |
| 19 | msr_t deftype = {0, 0}; |
| 20 | int mtrr; |
| 21 | |
| 22 | /* Disable fixed and variable MTRRs while we setup */ |
| 23 | wrmsr(MTRR_DEF_TYPE_MSR, deftype); |
| 24 | |
| 25 | clear_all_var_mtrr(); |
| 26 | |
| 27 | mtrr = get_free_var_mtrr(); |
| 28 | if (mtrr >= 0) |
| 29 | set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
| 30 | |
| 31 | mtrr = get_free_var_mtrr(); |
| 32 | if (mtrr >= 0) |
| 33 | set_var_mtrr(mtrr, (unsigned int)_bootblock, REGION_SIZE(bootblock), |
| 34 | MTRR_TYPE_WRBACK); |
| 35 | |
| 36 | /* Enable variable MTRRs. Fixed MTRRs are left disabled since they are not used. */ |
| 37 | deftype.lo |= MTRR_DEF_TYPE_EN | MTRR_TYPE_UNCACHEABLE; |
| 38 | wrmsr(MTRR_DEF_TYPE_MSR, deftype); |
| 39 | |
| 40 | enable_cache(); |
| 41 | } |
| 42 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 43 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
| 44 | { |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame^] | 45 | set_caching(); |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 46 | enable_pci_mmconf(); |
| 47 | |
| 48 | bootblock_main_with_basetime(base_timestamp); |
| 49 | } |
| 50 | |
| 51 | void bootblock_soc_early_init(void) |
| 52 | { |
| 53 | sb_reset_i2c_slaves(); |
| 54 | fch_pre_init(); |
| 55 | } |
| 56 | |
| 57 | void bootblock_soc_init(void) |
| 58 | { |
| 59 | u32 val = cpuid_eax(1); |
| 60 | printk(BIOS_DEBUG, "Family_Model: %08x\n", val); |
| 61 | |
| 62 | fch_early_init(); |
| 63 | i2c_soc_early_init(); |
| 64 | } |