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review.coreboot.org / coreboot / 4cb8776c31ceb4a5b9e353b2e9b2a4f751e1dc54 / . / src / mainboard / intel / adlrvp / memory.c
blob: b203f69240d68d08429f8546ef28b127c984938d [file] [log] [blame]
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <arch/cpu.h>
Subrata Banik0a61ece2020-11-07 13:01:49 +0530[diff] [blame]4#include "board_id.h"
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]5#include <baseboard/variants.h>
6#include <soc/romstage.h>
7
Subrata Banikb544fe42020-10-28 13:25:06 +0530[diff] [blame]8static const struct mb_cfg ddr4_mem_config = {
9 /* Baseboard uses only 100ohm Rcomp resistors */
10 .rcomp_resistor = {100, 100, 100},
11
12 /* Baseboard Rcomp target values */
13 .rcomp_targets = {40, 30, 33, 33, 30},
14
Subrata Banik3a873b52020-11-27 00:20:18 +0530[diff] [blame]15 .dq_pins_interleaved = false,
Subrata Banikb544fe42020-10-28 13:25:06 +0530[diff] [blame]16
17 .ect = true, /* Early Command Training */
18
19 .UserBd = BOARD_TYPE_MOBILE,
20};
21
22static const struct mb_cfg lpddr4_mem_config = {
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]23 /* DQ byte map */
24 .dq_map = {
Subrata Banik4cb87762020-11-27 00:16:46 +0530[diff] [blame^]25 { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 },
26 { 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 },
27 { 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 },
28 { 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 },
29 { 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 },
30 { 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 },
31 { 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 },
32 { 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 },
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]33 },
34
35 /* DQS CPU<>DRAM map */
36 .dqs_map = {
Subrata Banik4cb87762020-11-27 00:16:46 +0530[diff] [blame^]37 { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]38 },
39
Subrata Banikb544fe42020-10-28 13:25:06 +0530[diff] [blame]40 .dq_pins_interleaved = false,
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]41
42 .ect = true, /* Early Command Training */
43
44 .UserBd = BOARD_TYPE_MOBILE,
45};
46
Subrata Banik70296652020-10-28 13:50:19 +0530[diff] [blame]47static const struct mb_cfg ddr5_mem_config = {
48 /* Baseboard uses only 100ohm Rcomp resistors */
49 .rcomp_resistor = {100, 100, 100},
50
51 /* Baseboard Rcomp target values */
52 .rcomp_targets = {50, 30, 30, 30, 27},
53
Subrata Banik3a873b52020-11-27 00:20:18 +0530[diff] [blame]54 .dq_pins_interleaved = false,
Subrata Banik70296652020-10-28 13:50:19 +0530[diff] [blame]55
56 .ect = true, /* Early Command Training */
57
58 .UserBd = BOARD_TYPE_MOBILE,
59};
60
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]61const struct mb_cfg *variant_memory_params(void)
62{
Subrata Banikb544fe42020-10-28 13:25:06 +0530[diff] [blame]63 int board_id = get_board_id();
64
Sridhar Siricillac046dd02020-10-30 11:45:24 +0530[diff] [blame]65 switch (board_id) {
66 case ADL_P_LP4_1:
67 case ADL_P_LP4_2:
Subrata Banikb544fe42020-10-28 13:25:06 +0530[diff] [blame]68 return &lpddr4_mem_config;
Sridhar Siricillac046dd02020-10-30 11:45:24 +0530[diff] [blame]69 case ADL_P_DDR4_1:
70 case ADL_P_DDR4_2:
Subrata Banikb544fe42020-10-28 13:25:06 +0530[diff] [blame]71 return &ddr4_mem_config;
Sridhar Siricillac046dd02020-10-30 11:45:24 +0530[diff] [blame]72 case ADL_P_DDR5:
Subrata Banik70296652020-10-28 13:50:19 +0530[diff] [blame]73 return &ddr5_mem_config;
Sridhar Siricillac046dd02020-10-30 11:45:24 +0530[diff] [blame]74 default:
75 die("unsupported board id : 0x%x\n", board_id);
76 }
Subrata Banik16e41062020-10-06 20:13:06 +0530[diff] [blame]77}