Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef REG_SCRIPT_H |
| 17 | #define REG_SCRIPT_H |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/resource.h> |
| 23 | |
| 24 | /* |
| 25 | * The reg script library is a way to provide data-driven I/O accesses for |
| 26 | * initializing devices. It currently supports PCI, legacy I/O, |
| 27 | * memory-mapped I/O, and IOSF accesses. |
| 28 | * |
| 29 | * In order to simplify things for the developer the following features |
| 30 | * are employed: |
| 31 | * - Chaining of tables that allow runtime tables to chain to compile-time |
| 32 | * tables. |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 33 | * |
| 34 | * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push |
| 35 | * and pop of the context. A chained reg_script inherits the previous |
| 36 | * context (such as current device), but it does not impact the previous |
| 37 | * context in any way. |
| 38 | */ |
| 39 | |
| 40 | enum { |
| 41 | REG_SCRIPT_COMMAND_READ, |
| 42 | REG_SCRIPT_COMMAND_WRITE, |
| 43 | REG_SCRIPT_COMMAND_RMW, |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 44 | REG_SCRIPT_COMMAND_RXW, |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 45 | REG_SCRIPT_COMMAND_POLL, |
| 46 | REG_SCRIPT_COMMAND_SET_DEV, |
| 47 | REG_SCRIPT_COMMAND_NEXT, |
Lee Leahy | 564dc9c | 2016-04-29 15:07:19 -0700 | [diff] [blame] | 48 | REG_SCRIPT_COMMAND_DISPLAY, |
| 49 | |
| 50 | /* Insert new types above this comment */ |
| 51 | |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 52 | REG_SCRIPT_COMMAND_END, |
| 53 | }; |
| 54 | |
| 55 | enum { |
| 56 | REG_SCRIPT_TYPE_PCI, |
| 57 | REG_SCRIPT_TYPE_IO, |
| 58 | REG_SCRIPT_TYPE_MMIO, |
| 59 | REG_SCRIPT_TYPE_RES, |
| 60 | REG_SCRIPT_TYPE_IOSF, |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 61 | REG_SCRIPT_TYPE_MSR, |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 62 | |
| 63 | /* Insert other platform independent values above this comment */ |
| 64 | |
Lee Leahy | efcee9f | 2016-04-29 17:26:36 -0700 | [diff] [blame] | 65 | REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000, |
| 66 | REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE, |
| 67 | REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000 |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | enum { |
| 71 | REG_SCRIPT_SIZE_8, |
| 72 | REG_SCRIPT_SIZE_16, |
| 73 | REG_SCRIPT_SIZE_32, |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 74 | REG_SCRIPT_SIZE_64, |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | struct reg_script { |
| 78 | uint32_t command; |
| 79 | uint32_t type; |
| 80 | uint32_t size; |
| 81 | uint32_t reg; |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 82 | uint64_t mask; |
| 83 | uint64_t value; |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 84 | uint32_t timeout; |
| 85 | union { |
| 86 | uint32_t id; |
| 87 | const struct reg_script *next; |
Elyes HAOUAS | f9e47cc | 2018-12-05 11:03:36 +0100 | [diff] [blame] | 88 | #ifdef __SIMPLE_DEVICE__ |
| 89 | pci_devfn_t dev; |
| 90 | #else |
| 91 | struct device *dev; |
| 92 | #endif |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 93 | unsigned int res_index; |
| 94 | }; |
| 95 | }; |
| 96 | |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 97 | struct reg_script_context { |
Elyes HAOUAS | f9e47cc | 2018-12-05 11:03:36 +0100 | [diff] [blame] | 98 | #ifdef __SIMPLE_DEVICE__ |
| 99 | pci_devfn_t dev; |
| 100 | #else |
| 101 | struct device *dev; |
| 102 | #endif |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 103 | struct resource *res; |
| 104 | const struct reg_script *step; |
Lee Leahy | 564dc9c | 2016-04-29 15:07:19 -0700 | [diff] [blame] | 105 | uint8_t display_state; /* Only modified by reg_script_run_step */ |
| 106 | uint8_t display_features; /* Step routine modifies to control display */ |
| 107 | const char *display_prefix; /* Prefix tag to display */ |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 108 | }; |
| 109 | |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 110 | struct reg_script_bus_entry { |
Lee Leahy | efcee9f | 2016-04-29 17:26:36 -0700 | [diff] [blame] | 111 | uint32_t type; |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 112 | uint64_t (*reg_script_read)(struct reg_script_context *ctx); |
| 113 | void (*reg_script_write)(struct reg_script_context *ctx); |
| 114 | }; |
| 115 | |
Stefan Reinauer | 6a00113 | 2017-07-13 02:20:27 +0200 | [diff] [blame] | 116 | #define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__((used, section(".rsbe_init"))) |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 117 | |
Lee Leahy | efcee9f | 2016-04-29 17:26:36 -0700 | [diff] [blame] | 118 | #define REG_SCRIPT_BUS_ENTRY(bus_entry_) \ |
Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 119 | const struct reg_script_bus_entry *rsbe_ ## bus_entry_ \ |
Lee Leahy | efcee9f | 2016-04-29 17:26:36 -0700 | [diff] [blame] | 120 | REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_; |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 121 | |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 122 | /* Internal helper Macros. */ |
| 123 | |
| 124 | #define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \ |
| 125 | mask_, value_, timeout_, id_) \ |
| 126 | { .command = cmd_, \ |
| 127 | .type = type_, \ |
| 128 | .size = size_, \ |
| 129 | .reg = reg_, \ |
| 130 | .mask = mask_, \ |
| 131 | .value = value_, \ |
| 132 | .timeout = timeout_, \ |
| 133 | .id = id_, \ |
| 134 | } |
| 135 | |
| 136 | #define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \ |
| 137 | mask_, value_, timeout_) \ |
| 138 | { .command = cmd_, \ |
| 139 | .type = type_, \ |
| 140 | .size = size_, \ |
| 141 | .reg = reg_, \ |
| 142 | .mask = mask_, \ |
| 143 | .value = value_, \ |
| 144 | .timeout = timeout_, \ |
| 145 | .res_index = res_index_, \ |
| 146 | } |
| 147 | |
Lee Leahy | 564dc9c | 2016-04-29 15:07:19 -0700 | [diff] [blame] | 148 | /* Display control */ |
| 149 | #define REG_SCRIPT_DISPLAY_ALL 0xff |
| 150 | #define REG_SCRIPT_DISPLAY_REGISTER 0x02 |
| 151 | #define REG_SCRIPT_DISPLAY_VALUE 0x01 |
| 152 | #define REG_SCRIPT_DISPLAY_NOTHING 0 |
| 153 | |
| 154 | #define REG_SCRIPT_DISPLAY_OFF \ |
| 155 | { .command = REG_SCRIPT_COMMAND_DISPLAY, \ |
| 156 | .value = REG_SCRIPT_DISPLAY_NOTHING, \ |
| 157 | } |
| 158 | #define REG_SCRIPT_DISPLAY_ON \ |
| 159 | { .command = REG_SCRIPT_COMMAND_DISPLAY, \ |
| 160 | .value = REG_SCRIPT_DISPLAY_ALL, \ |
| 161 | } |
| 162 | |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 163 | /* |
| 164 | * PCI |
| 165 | */ |
| 166 | |
| 167 | #define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \ |
| 168 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 169 | REG_SCRIPT_TYPE_PCI, \ |
| 170 | REG_SCRIPT_SIZE_##bits_, \ |
| 171 | reg_, mask_, value_, timeout_, 0) |
| 172 | #define REG_PCI_READ8(reg_) \ |
| 173 | REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0) |
| 174 | #define REG_PCI_READ16(reg_) \ |
| 175 | REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0) |
| 176 | #define REG_PCI_READ32(reg_) \ |
| 177 | REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0) |
| 178 | #define REG_PCI_WRITE8(reg_, value_) \ |
| 179 | REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0) |
| 180 | #define REG_PCI_WRITE16(reg_, value_) \ |
| 181 | REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0) |
| 182 | #define REG_PCI_WRITE32(reg_, value_) \ |
| 183 | REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0) |
| 184 | #define REG_PCI_RMW8(reg_, mask_, value_) \ |
| 185 | REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0) |
| 186 | #define REG_PCI_RMW16(reg_, mask_, value_) \ |
| 187 | REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0) |
| 188 | #define REG_PCI_RMW32(reg_, mask_, value_) \ |
| 189 | REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 190 | #define REG_PCI_RXW8(reg_, mask_, value_) \ |
| 191 | REG_SCRIPT_PCI(RXW, 8, reg_, mask_, value_, 0) |
| 192 | #define REG_PCI_RXW16(reg_, mask_, value_) \ |
| 193 | REG_SCRIPT_PCI(RXW, 16, reg_, mask_, value_, 0) |
| 194 | #define REG_PCI_RXW32(reg_, mask_, value_) \ |
| 195 | REG_SCRIPT_PCI(RXW, 32, reg_, mask_, value_, 0) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 196 | #define REG_PCI_OR8(reg_, value_) \ |
| 197 | REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0) |
| 198 | #define REG_PCI_OR16(reg_, value_) \ |
| 199 | REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0) |
| 200 | #define REG_PCI_OR32(reg_, value_) \ |
| 201 | REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0) |
| 202 | #define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \ |
| 203 | REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_) |
| 204 | #define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \ |
| 205 | REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_) |
| 206 | #define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \ |
| 207 | REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 208 | #define REG_PCI_XOR8(reg_, value_) \ |
| 209 | REG_SCRIPT_PCI(RXW, 8, reg_, 0xff, value_, 0) |
| 210 | #define REG_PCI_XOR16(reg_, value_) \ |
| 211 | REG_SCRIPT_PCI(RXW, 16, reg_, 0xffff, value_, 0) |
| 212 | #define REG_PCI_XOR32(reg_, value_) \ |
| 213 | REG_SCRIPT_PCI(RXW, 32, reg_, 0xffffffff, value_, 0) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 214 | |
| 215 | /* |
| 216 | * Legacy IO |
| 217 | */ |
| 218 | |
| 219 | #define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \ |
| 220 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 221 | REG_SCRIPT_TYPE_IO, \ |
| 222 | REG_SCRIPT_SIZE_##bits_, \ |
| 223 | reg_, mask_, value_, timeout_, 0) |
| 224 | #define REG_IO_READ8(reg_) \ |
| 225 | REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0) |
| 226 | #define REG_IO_READ16(reg_) \ |
| 227 | REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0) |
| 228 | #define REG_IO_READ32(reg_) \ |
| 229 | REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0) |
| 230 | #define REG_IO_WRITE8(reg_, value_) \ |
| 231 | REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0) |
| 232 | #define REG_IO_WRITE16(reg_, value_) \ |
| 233 | REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0) |
| 234 | #define REG_IO_WRITE32(reg_, value_) \ |
| 235 | REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0) |
| 236 | #define REG_IO_RMW8(reg_, mask_, value_) \ |
| 237 | REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0) |
| 238 | #define REG_IO_RMW16(reg_, mask_, value_) \ |
| 239 | REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0) |
| 240 | #define REG_IO_RMW32(reg_, mask_, value_) \ |
| 241 | REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 242 | #define REG_IO_RXW8(reg_, mask_, value_) \ |
| 243 | REG_SCRIPT_IO(RXW, 8, reg_, mask_, value_, 0) |
| 244 | #define REG_IO_RXW16(reg_, mask_, value_) \ |
| 245 | REG_SCRIPT_IO(RXW, 16, reg_, mask_, value_, 0) |
| 246 | #define REG_IO_RXW32(reg_, mask_, value_) \ |
| 247 | REG_SCRIPT_IO(RXW, 32, reg_, mask_, value_, 0) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 248 | #define REG_IO_OR8(reg_, value_) \ |
Duncan Laurie | 21fd2f4 | 2014-04-22 11:14:12 -0700 | [diff] [blame] | 249 | REG_IO_RMW8(reg_, 0xff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 250 | #define REG_IO_OR16(reg_, value_) \ |
Duncan Laurie | 21fd2f4 | 2014-04-22 11:14:12 -0700 | [diff] [blame] | 251 | REG_IO_RMW16(reg_, 0xffff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 252 | #define REG_IO_OR32(reg_, value_) \ |
Duncan Laurie | 21fd2f4 | 2014-04-22 11:14:12 -0700 | [diff] [blame] | 253 | REG_IO_RMW32(reg_, 0xffffffff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 254 | #define REG_IO_POLL8(reg_, mask_, value_, timeout_) \ |
| 255 | REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_) |
| 256 | #define REG_IO_POLL16(reg_, mask_, value_, timeout_) \ |
| 257 | REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_) |
| 258 | #define REG_IO_POLL32(reg_, mask_, value_, timeout_) \ |
| 259 | REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 260 | #define REG_IO_XOR8(reg_, value_) \ |
| 261 | REG_IO_RXW8(reg_, 0xff, value_) |
| 262 | #define REG_IO_XOR16(reg_, value_) \ |
| 263 | REG_IO_RXW16(reg_, 0xffff, value_) |
| 264 | #define REG_IO_XOR32(reg_, value_) \ |
| 265 | REG_IO_RXW32(reg_, 0xffffffff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 266 | |
| 267 | /* |
| 268 | * Memory Mapped IO |
| 269 | */ |
| 270 | |
| 271 | #define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \ |
| 272 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 273 | REG_SCRIPT_TYPE_MMIO, \ |
| 274 | REG_SCRIPT_SIZE_##bits_, \ |
| 275 | reg_, mask_, value_, timeout_, 0) |
| 276 | #define REG_MMIO_READ8(reg_) \ |
| 277 | REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0) |
| 278 | #define REG_MMIO_READ16(reg_) \ |
| 279 | REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0) |
| 280 | #define REG_MMIO_READ32(reg_) \ |
| 281 | REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0) |
| 282 | #define REG_MMIO_WRITE8(reg_, value_) \ |
| 283 | REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0) |
| 284 | #define REG_MMIO_WRITE16(reg_, value_) \ |
| 285 | REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0) |
| 286 | #define REG_MMIO_WRITE32(reg_, value_) \ |
| 287 | REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0) |
| 288 | #define REG_MMIO_RMW8(reg_, mask_, value_) \ |
| 289 | REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0) |
| 290 | #define REG_MMIO_RMW16(reg_, mask_, value_) \ |
| 291 | REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0) |
| 292 | #define REG_MMIO_RMW32(reg_, mask_, value_) \ |
| 293 | REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 294 | #define REG_MMIO_RXW8(reg_, mask_, value_) \ |
| 295 | REG_SCRIPT_MMIO(RXW, 8, reg_, mask_, value_, 0) |
| 296 | #define REG_MMIO_RXW16(reg_, mask_, value_) \ |
| 297 | REG_SCRIPT_MMIO(RXW, 16, reg_, mask_, value_, 0) |
| 298 | #define REG_MMIO_RXW32(reg_, mask_, value_) \ |
| 299 | REG_SCRIPT_MMIO(RXW, 32, reg_, mask_, value_, 0) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 300 | #define REG_MMIO_OR8(reg_, value_) \ |
| 301 | REG_MMIO_RMW8(reg_, 0xff, value_) |
| 302 | #define REG_MMIO_OR16(reg_, value_) \ |
| 303 | REG_MMIO_RMW16(reg_, 0xffff, value_) |
| 304 | #define REG_MMIO_OR32(reg_, value_) \ |
| 305 | REG_MMIO_RMW32(reg_, 0xffffffff, value_) |
| 306 | #define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \ |
| 307 | REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_) |
| 308 | #define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \ |
| 309 | REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_) |
| 310 | #define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \ |
| 311 | REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 312 | #define REG_MMIO_XOR8(reg_, value_) \ |
| 313 | REG_MMIO_RXW8(reg_, 0xff, value_) |
| 314 | #define REG_MMIO_XOR16(reg_, value_) \ |
| 315 | REG_MMIO_RXW16(reg_, 0xffff, value_) |
| 316 | #define REG_MMIO_XOR32(reg_, value_) \ |
| 317 | REG_MMIO_RXW32(reg_, 0xffffffff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 318 | |
| 319 | /* |
| 320 | * Access through a device's resource such as a Base Address Register (BAR) |
| 321 | */ |
| 322 | |
| 323 | #define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \ |
| 324 | _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \ |
| 325 | REG_SCRIPT_TYPE_RES, bar_, \ |
| 326 | REG_SCRIPT_SIZE_##bits_, \ |
| 327 | reg_, mask_, value_, timeout_) |
| 328 | #define REG_RES_READ8(bar_, reg_) \ |
| 329 | REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0) |
| 330 | #define REG_RES_READ16(bar_, reg_) \ |
| 331 | REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0) |
| 332 | #define REG_RES_READ32(bar_, reg_) \ |
| 333 | REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0) |
| 334 | #define REG_RES_WRITE8(bar_, reg_, value_) \ |
| 335 | REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0) |
| 336 | #define REG_RES_WRITE16(bar_, reg_, value_) \ |
| 337 | REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0) |
| 338 | #define REG_RES_WRITE32(bar_, reg_, value_) \ |
| 339 | REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0) |
| 340 | #define REG_RES_RMW8(bar_, reg_, mask_, value_) \ |
| 341 | REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0) |
| 342 | #define REG_RES_RMW16(bar_, reg_, mask_, value_) \ |
| 343 | REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0) |
| 344 | #define REG_RES_RMW32(bar_, reg_, mask_, value_) \ |
| 345 | REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 346 | #define REG_RES_RXW8(bar_, reg_, mask_, value_) \ |
| 347 | REG_SCRIPT_RES(RXW, 8, bar_, reg_, mask_, value_, 0) |
| 348 | #define REG_RES_RXW16(bar_, reg_, mask_, value_) \ |
| 349 | REG_SCRIPT_RES(RXW, 16, bar_, reg_, mask_, value_, 0) |
| 350 | #define REG_RES_RXW32(bar_, reg_, mask_, value_) \ |
| 351 | REG_SCRIPT_RES(RXW, 32, bar_, reg_, mask_, value_, 0) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 352 | #define REG_RES_OR8(bar_, reg_, value_) \ |
| 353 | REG_RES_RMW8(bar_, reg_, 0xff, value_) |
| 354 | #define REG_RES_OR16(bar_, reg_, value_) \ |
| 355 | REG_RES_RMW16(bar_, reg_, 0xffff, value_) |
| 356 | #define REG_RES_OR32(bar_, reg_, value_) \ |
| 357 | REG_RES_RMW32(bar_, reg_, 0xffffffff, value_) |
| 358 | #define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \ |
| 359 | REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_) |
| 360 | #define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \ |
| 361 | REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_) |
| 362 | #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ |
| 363 | REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 364 | #define REG_RES_XOR8(bar_, reg_, value_) \ |
| 365 | REG_RES_RXW8(bar_, reg_, 0xff, value_) |
| 366 | #define REG_RES_XOR16(bar_, reg_, value_) \ |
| 367 | REG_RES_RXW16(bar_, reg_, 0xffff, value_) |
| 368 | #define REG_RES_XOR32(bar_, reg_, value_) \ |
| 369 | REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 370 | |
Lee Leahy | 9f5a5c5 | 2014-08-29 13:38:59 -0700 | [diff] [blame] | 371 | |
Werner Zeh | 9d02153 | 2016-02-19 10:02:49 +0100 | [diff] [blame] | 372 | #if IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \ |
| 373 | IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 374 | /* |
| 375 | * IO Sideband Function |
| 376 | */ |
| 377 | |
| 378 | #define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \ |
| 379 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 380 | REG_SCRIPT_TYPE_IOSF, \ |
| 381 | REG_SCRIPT_SIZE_32, \ |
| 382 | reg_, mask_, value_, timeout_, unit_) |
| 383 | #define REG_IOSF_READ(unit_, reg_) \ |
| 384 | REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0) |
| 385 | #define REG_IOSF_WRITE(unit_, reg_, value_) \ |
| 386 | REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) |
| 387 | #define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ |
| 388 | REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 389 | #define REG_IOSF_RXW(unit_, reg_, mask_, value_) \ |
| 390 | REG_SCRIPT_IOSF(RXW, unit_, reg_, mask_, value_, 0) |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 391 | #define REG_IOSF_OR(unit_, reg_, value_) \ |
| 392 | REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) |
| 393 | #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ |
| 394 | REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 395 | #define REG_IOSF_XOR(unit_, reg_, value_) \ |
| 396 | REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_) |
Werner Zeh | 9d02153 | 2016-02-19 10:02:49 +0100 | [diff] [blame] | 397 | #endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/ |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 398 | |
| 399 | /* |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 400 | * CPU Model Specific Register |
| 401 | */ |
| 402 | |
| 403 | #define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \ |
| 404 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ |
| 405 | REG_SCRIPT_TYPE_MSR, \ |
| 406 | REG_SCRIPT_SIZE_64, \ |
| 407 | reg_, mask_, value_, timeout_, 0) |
| 408 | #define REG_MSR_READ(reg_) \ |
| 409 | REG_SCRIPT_MSR(READ, reg_, 0, 0, 0) |
| 410 | #define REG_MSR_WRITE(reg_, value_) \ |
| 411 | REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) |
| 412 | #define REG_MSR_RMW(reg_, mask_, value_) \ |
| 413 | REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 414 | #define REG_MSR_RXW(reg_, mask_, value_) \ |
| 415 | REG_SCRIPT_MSR(RXW, reg_, mask_, value_, 0) |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 416 | #define REG_MSR_OR(reg_, value_) \ |
| 417 | REG_MSR_RMW(reg_, -1ULL, value_) |
| 418 | #define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ |
| 419 | REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) |
Lee Leahy | 6bcbe57 | 2016-04-23 07:58:27 -0700 | [diff] [blame] | 420 | #define REG_MSR_XOR(reg_, value_) \ |
| 421 | REG_MSR_RXW(reg_, -1ULL, value_) |
Duncan Laurie | fd461e3 | 2013-11-08 23:00:24 -0800 | [diff] [blame] | 422 | |
| 423 | /* |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 424 | * Chain to another table. |
| 425 | */ |
| 426 | #define REG_SCRIPT_NEXT(next_) \ |
| 427 | { .command = REG_SCRIPT_COMMAND_NEXT, \ |
| 428 | .next = next_, \ |
| 429 | } |
| 430 | |
| 431 | /* |
| 432 | * Set current device |
| 433 | */ |
| 434 | #define REG_SCRIPT_SET_DEV(dev_) \ |
| 435 | { .command = REG_SCRIPT_COMMAND_SET_DEV, \ |
| 436 | .dev = dev_, \ |
| 437 | } |
| 438 | |
| 439 | /* |
| 440 | * Last script entry. All tables need to end with REG_SCRIPT_END. |
| 441 | */ |
| 442 | #define REG_SCRIPT_END \ |
| 443 | _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) |
| 444 | |
| 445 | void reg_script_run(const struct reg_script *script); |
Elyes HAOUAS | f9e47cc | 2018-12-05 11:03:36 +0100 | [diff] [blame] | 446 | #ifdef __SIMPLE_DEVICE__ |
| 447 | void reg_script_run_on_dev(pci_devfn_t dev, const struct reg_script *step); |
| 448 | #else |
| 449 | void reg_script_run_on_dev(struct device *dev, const struct reg_script *step); |
| 450 | #endif |
Duncan Laurie | 7274800 | 2013-10-31 08:26:23 -0700 | [diff] [blame] | 451 | |
| 452 | #endif /* REG_SCRIPT_H */ |