Macpaul Lin | 577766e | 2022-08-11 18:46:06 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/mmio.h> |
| 5 | #include <delay.h> |
| 6 | #include <stddef.h> |
| 7 | #include <timer.h> |
| 8 | |
| 9 | #include <soc/addressmap.h> |
| 10 | #include <soc/infracfg.h> |
| 11 | #include <soc/mcucfg.h> |
| 12 | #include <soc/pll.h> |
| 13 | #include <soc/spm.h> |
| 14 | #include <soc/wdt.h> |
| 15 | |
| 16 | enum mux_id { |
| 17 | TOP_AXI_SEL, |
| 18 | TOP_SPM_SEL, |
| 19 | TOP_SCP_SEL, |
| 20 | TOP_BUS_AXIMEM_SEL, |
| 21 | TOP_VPP_SEL, |
| 22 | TOP_ETHDR_SEL, |
| 23 | TOP_IPE_SEL, |
| 24 | TOP_CAM_SEL, |
| 25 | TOP_CCU_SEL, |
| 26 | TOP_CCU_AHB_SEL, |
| 27 | TOP_IMG_SEL, |
| 28 | TOP_CAMTM_SEL, |
| 29 | TOP_DSP_SEL, |
| 30 | TOP_DSP1_SEL, |
| 31 | TOP_DSP2_SEL, |
| 32 | TOP_DSP3_SEL, |
| 33 | TOP_DSP4_SEL, |
| 34 | TOP_DSP5_SEL, |
| 35 | TOP_DSP6_SEL, |
| 36 | TOP_DSP7_SEL, |
| 37 | TOP_MFG_CORE_TMP_SEL, |
| 38 | TOP_CAMTG_SEL, |
| 39 | TOP_CAMTG2_SEL, |
| 40 | TOP_CAMTG3_SEL, |
| 41 | TOP_UART_SEL, |
| 42 | TOP_SPI_SEL, |
| 43 | TOP_MSDC50_0_HSEL, |
| 44 | TOP_MSDC50_0_SEL, |
| 45 | TOP_MSDC30_1_SEL, |
| 46 | TOP_MSDC30_2_SEL, |
| 47 | TOP_INTDIR_SEL, |
| 48 | TOP_AUD_INTBUS_SEL, |
| 49 | TOP_AUDIO_H_SEL, |
| 50 | TOP_PWRAP_ULPOSC_SEL, |
| 51 | TOP_ATB_SEL, |
| 52 | TOP_SSPM_SEL, |
| 53 | TOP_DP_SEL, |
| 54 | TOP_EDP_SEL, |
| 55 | TOP_DPI_SEL, |
| 56 | TOP_DISP_PWM0_SEL, |
| 57 | TOP_DISP_PWM1_SEL, |
| 58 | TOP_USB_TOP_SEL, |
| 59 | TOP_SSUSB_XHCI_SEL, |
| 60 | TOP_USB_TOP_2P_SEL, |
| 61 | TOP_SSUSB_XHCI_2P_SEL, |
| 62 | TOP_USB_TOP_3P_SEL, |
| 63 | TOP_SSUSB_XHCI_3P_SEL, |
| 64 | TOP_I2C_SEL, |
| 65 | TOP_SENINF_SEL, |
| 66 | TOP_SENINF1_SEL, |
| 67 | TOP_GCPU_SEL, |
| 68 | TOP_VENC_SEL, |
| 69 | TOP_VDEC_SEL, |
| 70 | TOP_PWM_SEL, |
| 71 | TOP_MCUPM_SEL, |
| 72 | TOP_SPMI_P_MST_SEL, |
| 73 | TOP_SPMI_M_MST_SEL, |
| 74 | TOP_DVFSRC_SEL, |
| 75 | TOP_TL_SEL, |
| 76 | TOP_AES_MSDCFDE_SEL, |
| 77 | TOP_DSI_OCC_SEL, |
| 78 | TOP_WPE_VPP_SEL, |
| 79 | TOP_HDCP_SEL, |
| 80 | TOP_HDCP_24M_SEL, |
| 81 | TOP_HDMI_APB_SEL, |
| 82 | TOP_SNPS_ETH_250M_SEL, |
| 83 | TOP_SNPS_ETH_62P4M_PTP_SEL, |
| 84 | TOP_SNPS_ETH_50M_RMII_SEL, |
| 85 | TOP_ADSP_SEL, |
| 86 | TOP_AUDIO_LOCAL_BUS_SEL, |
| 87 | TOP_ASM_H_SEL, |
| 88 | TOP_ASM_L_SEL, |
| 89 | TOP_APLL1_SEL, |
| 90 | TOP_APLL2_SEL, |
| 91 | TOP_APLL3_SEL, |
| 92 | TOP_APLL4_SEL, |
| 93 | TOP_APLL5_SEL, |
| 94 | TOP_I2SO1_SEL, |
| 95 | TOP_I2SO2_SEL, |
| 96 | TOP_I2SI1_SEL, |
| 97 | TOP_I2SI2_SEL, |
| 98 | TOP_DPTX_SEL, |
| 99 | TOP_AUD_IEC_SEL, |
| 100 | TOP_A1SYS_HP_SEL, |
| 101 | TOP_A2SYS_SEL, |
| 102 | TOP_A3SYS_SEL, |
| 103 | TOP_A4SYS_SEL, |
| 104 | TOP_ECC_SEL, |
| 105 | TOP_SPINOR_SEL, |
| 106 | TOP_ULPOSC_SEL, |
| 107 | TOP_SRCK_SEL, |
| 108 | TOP_MFG_CK_FAST_REF_SEL, |
| 109 | TOP_NR_MUX |
| 110 | }; |
| 111 | |
| 112 | #define MUX(_id, _reg, _mux_shift, _mux_width) \ |
| 113 | [_id] = { \ |
| 114 | .reg = &mtk_topckgen->_reg, \ |
| 115 | .mux_shift = _mux_shift, \ |
| 116 | .mux_width = _mux_width, \ |
| 117 | } |
| 118 | |
| 119 | #define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\ |
| 120 | [_id] = { \ |
| 121 | .reg = &mtk_topckgen->_reg, \ |
| 122 | .set_reg = &mtk_topckgen->_reg##_set, \ |
| 123 | .clr_reg = &mtk_topckgen->_reg##_clr, \ |
| 124 | .mux_shift = _mux_shift, \ |
| 125 | .mux_width = _mux_width, \ |
| 126 | .upd_reg = &mtk_topckgen->_upd_reg, \ |
| 127 | .upd_shift = _upd_shift, \ |
| 128 | } |
| 129 | |
| 130 | static const struct mux muxes[] = { |
| 131 | /* CLK_CFG_0 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 132 | MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 4, clk_cfg_update, 0), |
| 133 | MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 4, clk_cfg_update, 1), |
| 134 | MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 4, clk_cfg_update, 2), |
| 135 | MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 4, clk_cfg_update, 3), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 136 | /* CLK_CFG_1 */ |
| 137 | MUX_UPD(TOP_VPP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4), |
| 138 | MUX_UPD(TOP_ETHDR_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5), |
| 139 | MUX_UPD(TOP_IPE_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6), |
| 140 | MUX_UPD(TOP_CAM_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7), |
| 141 | /* CLK_CFG_2 */ |
| 142 | MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8), |
| 143 | MUX_UPD(TOP_CCU_AHB_SEL, clk_cfg_2, 8, 4, clk_cfg_update, 9), |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 144 | MUX_UPD(TOP_IMG_SEL, clk_cfg_2, 16, 4, clk_cfg_update, 10), |
| 145 | MUX_UPD(TOP_CAMTM_SEL, clk_cfg_2, 24, 4, clk_cfg_update, 11), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 146 | /* CLK_CFG_3 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 147 | MUX_UPD(TOP_DSP_SEL, clk_cfg_3, 0, 4, clk_cfg_update, 12), |
| 148 | MUX_UPD(TOP_DSP1_SEL, clk_cfg_3, 8, 4, clk_cfg_update, 13), |
| 149 | MUX_UPD(TOP_DSP2_SEL, clk_cfg_3, 16, 4, clk_cfg_update, 14), |
| 150 | MUX_UPD(TOP_DSP3_SEL, clk_cfg_3, 24, 4, clk_cfg_update, 15), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 151 | /* CLK_CFG_4 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 152 | MUX_UPD(TOP_DSP4_SEL, clk_cfg_4, 0, 4, clk_cfg_update, 16), |
| 153 | MUX_UPD(TOP_DSP5_SEL, clk_cfg_4, 8, 4, clk_cfg_update, 17), |
| 154 | MUX_UPD(TOP_DSP6_SEL, clk_cfg_4, 16, 4, clk_cfg_update, 18), |
| 155 | MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 24, 4, clk_cfg_update, 19), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 156 | /* CLK_CFG_5 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 157 | MUX_UPD(TOP_MFG_CORE_TMP_SEL, clk_cfg_5, 0, 4, clk_cfg_update, 20), |
| 158 | MUX_UPD(TOP_CAMTG_SEL, clk_cfg_5, 8, 4, clk_cfg_update, 21), |
| 159 | MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 16, 4, clk_cfg_update, 22), |
| 160 | MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 24, 4, clk_cfg_update, 23), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 161 | /* CLK_CFG_6 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 162 | MUX_UPD(TOP_UART_SEL, clk_cfg_6, 0, 4, clk_cfg_update, 24), |
| 163 | MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 8, 4, clk_cfg_update, 25), |
| 164 | MUX_UPD(TOP_MSDC50_0_HSEL, clk_cfg_6, 16, 4, clk_cfg_update, 26), |
| 165 | MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_6, 24, 4, clk_cfg_update, 27), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 166 | /* CLK_CFG_7 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 167 | MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 0, 4, clk_cfg_update, 28), |
| 168 | MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, 8, 4, clk_cfg_update, 29), |
| 169 | MUX_UPD(TOP_INTDIR_SEL, clk_cfg_7, 16, 4, clk_cfg_update, 30), |
| 170 | MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_7, 24, 4, clk_cfg_update, 31), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 171 | /* CLK_CFG_8 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 172 | MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_8, 0, 4, clk_cfg_update1, 0), |
| 173 | MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 8, 4, clk_cfg_update1, 1), |
| 174 | MUX_UPD(TOP_ATB_SEL, clk_cfg_8, 16, 4, clk_cfg_update1, 2), |
| 175 | MUX_UPD(TOP_SSPM_SEL, clk_cfg_8, 24, 4, clk_cfg_update1, 3), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 176 | /* CLK_CFG_9 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 177 | MUX_UPD(TOP_DP_SEL, clk_cfg_9, 0, 4, clk_cfg_update1, 4), |
| 178 | MUX_UPD(TOP_EDP_SEL, clk_cfg_9, 8, 4, clk_cfg_update1, 5), |
| 179 | MUX_UPD(TOP_DPI_SEL, clk_cfg_9, 16, 4, clk_cfg_update1, 6), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 180 | MUX_UPD(TOP_DISP_PWM0_SEL, clk_cfg_9, 24, 4, clk_cfg_update1, 7), |
| 181 | /* CLK_CFG_10 */ |
| 182 | MUX_UPD(TOP_DISP_PWM1_SEL, clk_cfg_10, 0, 4, clk_cfg_update1, 8), |
| 183 | MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_10, 8, 4, clk_cfg_update1, 9), |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 184 | MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, 16, 4, clk_cfg_update1, 10), |
| 185 | MUX_UPD(TOP_USB_TOP_2P_SEL, clk_cfg_10, 24, 4, clk_cfg_update1, 11), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 186 | /* CLK_CFG_11 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 187 | MUX_UPD(TOP_SSUSB_XHCI_2P_SEL, clk_cfg_11, 0, 4, clk_cfg_update1, 12), |
| 188 | MUX_UPD(TOP_USB_TOP_3P_SEL, clk_cfg_11, 8, 4, clk_cfg_update1, 13), |
| 189 | MUX_UPD(TOP_SSUSB_XHCI_3P_SEL, clk_cfg_11, 16, 4, clk_cfg_update1, 14), |
| 190 | MUX_UPD(TOP_I2C_SEL, clk_cfg_11, 24, 4, clk_cfg_update1, 15), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 191 | /* CLK_CFG_12 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 192 | MUX_UPD(TOP_SENINF_SEL, clk_cfg_12, 0, 4, clk_cfg_update1, 16), |
| 193 | MUX_UPD(TOP_SENINF1_SEL, clk_cfg_12, 8, 4, clk_cfg_update1, 17), |
| 194 | MUX_UPD(TOP_GCPU_SEL, clk_cfg_12, 16, 4, clk_cfg_update1, 18), |
| 195 | MUX_UPD(TOP_VENC_SEL, clk_cfg_12, 24, 4, clk_cfg_update1, 19), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 196 | /* CLK_CFG_13 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 197 | MUX_UPD(TOP_VDEC_SEL, clk_cfg_13, 0, 4, clk_cfg_update1, 20), |
| 198 | MUX_UPD(TOP_PWM_SEL, clk_cfg_13, 8, 4, clk_cfg_update1, 21), |
| 199 | MUX_UPD(TOP_MCUPM_SEL, clk_cfg_13, 16, 4, clk_cfg_update1, 22), |
| 200 | MUX_UPD(TOP_SPMI_P_MST_SEL, clk_cfg_13, 24, 4, clk_cfg_update1, 23), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 201 | /* CLK_CFG_14 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 202 | MUX_UPD(TOP_SPMI_M_MST_SEL, clk_cfg_14, 0, 4, clk_cfg_update1, 24), |
| 203 | MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_14, 8, 4, clk_cfg_update1, 25), |
| 204 | MUX_UPD(TOP_TL_SEL, clk_cfg_14, 16, 4, clk_cfg_update1, 26), |
| 205 | MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_14, 24, 4, clk_cfg_update1, 27), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 206 | /* CLK_CFG_15 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 207 | MUX_UPD(TOP_DSI_OCC_SEL, clk_cfg_15, 0, 4, clk_cfg_update1, 28), |
| 208 | MUX_UPD(TOP_WPE_VPP_SEL, clk_cfg_15, 8, 4, clk_cfg_update1, 29), |
| 209 | MUX_UPD(TOP_HDCP_SEL, clk_cfg_15, 16, 4, clk_cfg_update1, 30), |
| 210 | MUX_UPD(TOP_HDCP_24M_SEL, clk_cfg_15, 24, 4, clk_cfg_update1, 31), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 211 | /* CLK_CFG_16 */ |
| 212 | MUX_UPD(TOP_HDMI_APB_SEL, clk_cfg_16, 0, 4, clk_cfg_update2, 0), |
| 213 | MUX_UPD(TOP_SNPS_ETH_250M_SEL, clk_cfg_16, 8, 4, clk_cfg_update2, 1), |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 214 | MUX_UPD(TOP_SNPS_ETH_62P4M_PTP_SEL, clk_cfg_16, 16, 4, clk_cfg_update2, 2), |
| 215 | MUX_UPD(TOP_SNPS_ETH_50M_RMII_SEL, clk_cfg_16, 24, 4, clk_cfg_update2, 3), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 216 | /* CLK_CFG_17 */ |
| 217 | MUX_UPD(TOP_ADSP_SEL, clk_cfg_17, 0, 4, clk_cfg_update2, 4), |
| 218 | MUX_UPD(TOP_AUDIO_LOCAL_BUS_SEL, clk_cfg_17, 8, 4, clk_cfg_update2, 5), |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 219 | MUX_UPD(TOP_ASM_H_SEL, clk_cfg_17, 16, 4, clk_cfg_update2, 6), |
| 220 | MUX_UPD(TOP_ASM_L_SEL, clk_cfg_17, 24, 4, clk_cfg_update2, 7), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 221 | /* CLK_CFG_18 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 222 | MUX_UPD(TOP_APLL1_SEL, clk_cfg_18, 0, 4, clk_cfg_update2, 8), |
| 223 | MUX_UPD(TOP_APLL2_SEL, clk_cfg_18, 8, 4, clk_cfg_update2, 9), |
| 224 | MUX_UPD(TOP_APLL3_SEL, clk_cfg_18, 16, 4, clk_cfg_update2, 10), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 225 | MUX_UPD(TOP_APLL4_SEL, clk_cfg_18, 24, 4, clk_cfg_update2, 11), |
| 226 | /* CLK_CFG_19 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 227 | MUX_UPD(TOP_APLL5_SEL, clk_cfg_19, 0, 4, clk_cfg_update2, 12), |
| 228 | MUX_UPD(TOP_I2SO1_SEL, clk_cfg_19, 8, 4, clk_cfg_update2, 13), |
| 229 | MUX_UPD(TOP_I2SO2_SEL, clk_cfg_19, 16, 4, clk_cfg_update2, 14), |
| 230 | MUX_UPD(TOP_I2SI1_SEL, clk_cfg_19, 24, 4, clk_cfg_update2, 15), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 231 | /* CLK_CFG_20 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 232 | MUX_UPD(TOP_I2SI2_SEL, clk_cfg_20, 0, 4, clk_cfg_update2, 16), |
| 233 | MUX_UPD(TOP_DPTX_SEL, clk_cfg_20, 8, 4, clk_cfg_update2, 17), |
| 234 | MUX_UPD(TOP_AUD_IEC_SEL, clk_cfg_20, 16, 4, clk_cfg_update2, 18), |
| 235 | MUX_UPD(TOP_A1SYS_HP_SEL, clk_cfg_20, 24, 4, clk_cfg_update2, 19), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 236 | /* CLK_CFG_21 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 237 | MUX_UPD(TOP_A2SYS_SEL, clk_cfg_21, 0, 4, clk_cfg_update2, 20), |
| 238 | MUX_UPD(TOP_A3SYS_SEL, clk_cfg_21, 8, 4, clk_cfg_update2, 21), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 239 | MUX_UPD(TOP_A4SYS_SEL, clk_cfg_21, 16, 4, clk_cfg_update2, 22), |
| 240 | MUX_UPD(TOP_ECC_SEL, clk_cfg_21, 24, 4, clk_cfg_update2, 23), |
| 241 | /* CLK_CFG_22 */ |
| 242 | MUX_UPD(TOP_SPINOR_SEL, clk_cfg_22, 0, 4, clk_cfg_update2, 24), |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 243 | MUX_UPD(TOP_ULPOSC_SEL, clk_cfg_22, 8, 4, clk_cfg_update2, 25), |
| 244 | MUX_UPD(TOP_SRCK_SEL, clk_cfg_22, 16, 4, clk_cfg_update2, 26), |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | struct mux_sel { |
| 248 | enum mux_id id; |
| 249 | u32 sel; |
| 250 | }; |
| 251 | |
| 252 | static const struct mux_sel mux_sels[] = { |
| 253 | /* CLK_CFG_0 */ |
| 254 | { .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */ |
| 255 | { .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */ |
| 256 | { .id = TOP_SCP_SEL, .sel = 5 }, /* 5: mainpll_d4_d2 */ |
| 257 | { .id = TOP_BUS_AXIMEM_SEL, .sel = 1 }, /* 1: mainpll_d7_d2 */ |
| 258 | /* CLK_CFG_1 */ |
Hsiao Chien Sung | 4c0dc4e | 2023-03-31 12:56:08 +0800 | [diff] [blame^] | 259 | { .id = TOP_VPP_SEL, .sel = 11 }, /* 11: tvdpll1_ck */ |
Garmin Chang | c7b549e | 2022-09-12 18:00:21 +0800 | [diff] [blame] | 260 | { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 261 | { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 262 | { .id = TOP_CAM_SEL, .sel = 9 }, /* 9: mainpll_d4_d2 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 263 | /* CLK_CFG_2 */ |
| 264 | { .id = TOP_CCU_SEL, .sel = 2 }, /* 2: mainpll_d4_d2 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 265 | { .id = TOP_CCU_AHB_SEL, .sel = 2 }, /* 2: mainpll_d4_d2 */ |
| 266 | { .id = TOP_IMG_SEL, .sel = 11 }, /* 11: mainpll_d4_d2 */ |
| 267 | { .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 268 | /* CLK_CFG_3 */ |
| 269 | { .id = TOP_DSP_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
| 270 | { .id = TOP_DSP1_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
| 271 | { .id = TOP_DSP2_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
| 272 | { .id = TOP_DSP3_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
| 273 | /* CLK_CFG_4 */ |
| 274 | { .id = TOP_DSP4_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
| 275 | { .id = TOP_DSP5_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
| 276 | { .id = TOP_DSP6_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 277 | { .id = TOP_DSP7_SEL, .sel = 7 }, /* 7: univpll_d3 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 278 | /* CLK_CFG_5 */ |
| 279 | { .id = TOP_MFG_CORE_TMP_SEL, .sel = 3 }, /* 3: univpll_d7 */ |
| 280 | { .id = TOP_CAMTG_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */ |
| 281 | { .id = TOP_CAMTG2_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */ |
| 282 | { .id = TOP_CAMTG3_SEL, .sel = 2 }, /* 2: univpll_d6_d8 */ |
| 283 | /* CLK_CFG_6 */ |
| 284 | { .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */ |
| 285 | { .id = TOP_SPI_SEL, .sel = 4 }, /* 4: univpll_d6_d2 */ |
| 286 | { .id = TOP_MSDC50_0_HSEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ |
| 287 | { .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */ |
| 288 | /* CLK_CFG_7 */ |
| 289 | { .id = TOP_MSDC30_1_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ |
| 290 | { .id = TOP_MSDC30_2_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ |
| 291 | { .id = TOP_INTDIR_SEL, .sel = 3 }, /* 3: univpll_d4 */ |
| 292 | { .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ |
| 293 | /* CLK_CFG_8 */ |
| 294 | { .id = TOP_AUDIO_H_SEL, .sel = 2 }, /* 2: apll1_ck */ |
Garmin.Chang | f189249 | 2022-09-12 18:05:14 +0800 | [diff] [blame] | 295 | { .id = TOP_PWRAP_ULPOSC_SEL, .sel = 1 }, /* 1: ulposc_d10 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 296 | { .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */ |
| 297 | { .id = TOP_SSPM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ |
| 298 | /* CLK_CFG_9 */ |
| 299 | { .id = TOP_DP_SEL, .sel = 3 }, /* 3: tvdpll1_d4 */ |
| 300 | { .id = TOP_EDP_SEL, .sel = 4 }, /* 4: tvdpll2_d4 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 301 | { .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll1_d2 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 302 | { .id = TOP_DISP_PWM0_SEL, .sel = 2 }, /* 2: ulposc_d2 */ |
| 303 | /* CLK_CFG_10 */ |
| 304 | { .id = TOP_DISP_PWM1_SEL, .sel = 2 }, /* 2: ulposc_d2 */ |
| 305 | { .id = TOP_USB_TOP_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ |
| 306 | { .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */ |
| 307 | { .id = TOP_USB_TOP_2P_SEL, .sel = 1 }, /* 1: univpll_d6_d4 */ |
| 308 | /* CLK_CFG_11 */ |
| 309 | { .id = TOP_SSUSB_XHCI_2P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ |
| 310 | { .id = TOP_USB_TOP_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ |
| 311 | { .id = TOP_SSUSB_XHCI_3P_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */ |
| 312 | { .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */ |
| 313 | /* CLK_CFG_12 */ |
| 314 | { .id = TOP_SENINF_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ |
| 315 | { .id = TOP_SENINF1_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */ |
| 316 | { .id = TOP_GCPU_SEL, .sel = 3 }, /* 3: mmpll_d5_d2 */ |
| 317 | { .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */ |
| 318 | /* CLK_CFG_13 */ |
| 319 | { .id = TOP_VDEC_SEL, .sel = 1 }, /* 1: mainpll_d5_d2 */ |
| 320 | { .id = TOP_PWM_SEL, .sel = 3 }, /* 3: univpll_d6_d4 */ |
| 321 | { .id = TOP_MCUPM_SEL, .sel = 1 }, /* 1: mainpll_d6_d2 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 322 | { .id = TOP_SPMI_P_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 323 | /* CLK_CFG_14 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 324 | { .id = TOP_SPMI_M_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 325 | { .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */ |
| 326 | { .id = TOP_TL_SEL, .sel = 2 }, /* 2: mainpll_d4_d4 */ |
| 327 | { .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */ |
| 328 | /* CLK_CFG_15 */ |
| 329 | { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 330 | { .id = TOP_WPE_VPP_SEL, .sel = 4 }, /* 4: mainpll_d4_d2 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 331 | { .id = TOP_HDCP_SEL, .sel = 3 }, /* 3: univpll_d6_d4 */ |
| 332 | { .id = TOP_HDCP_24M_SEL, .sel = 1 }, /* 1: univpll_192m_d4 */ |
| 333 | /* CLK_CFG_16 */ |
| 334 | { .id = TOP_HDMI_APB_SEL, .sel = 2 }, /* 2: msdcpll_d2 */ |
| 335 | { .id = TOP_SNPS_ETH_250M_SEL, .sel = 1 }, /* 1: ethpll_d2 */ |
Garmin Chang | 1fac2e2 | 2022-09-12 18:06:07 +0800 | [diff] [blame] | 336 | { .id = TOP_SNPS_ETH_62P4M_PTP_SEL, .sel = 3 }, /* 3: ethpll_d8 */ |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 337 | { .id = TOP_SNPS_ETH_50M_RMII_SEL, .sel = 1 }, /* 1: ethpll_d10 */ |
| 338 | /* CLK_CFG_17 */ |
| 339 | { .id = TOP_ADSP_SEL, .sel = 8 }, /* 8: adsppll_ck */ |
| 340 | { .id = TOP_AUDIO_LOCAL_BUS_SEL, .sel = 4 }, /* 4: mainpll_d5_d2 */ |
| 341 | { .id = TOP_ASM_H_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ |
| 342 | { .id = TOP_ASM_L_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ |
| 343 | /* CLK_CFG_18 */ |
| 344 | { .id = TOP_APLL1_SEL, .sel = 1 }, /* 1: apll1_d4 */ |
| 345 | { .id = TOP_APLL2_SEL, .sel = 1 }, /* 1: apll2_d4 */ |
| 346 | { .id = TOP_APLL3_SEL, .sel = 1 }, /* 1: apll3_d4 */ |
| 347 | { .id = TOP_APLL4_SEL, .sel = 1 }, /* 1: apll4_d4 */ |
| 348 | /* CLK_CFG_19 */ |
| 349 | { .id = TOP_APLL5_SEL, .sel = 1 }, /* 1: apll5_d4 */ |
| 350 | { .id = TOP_I2SO1_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 351 | { .id = TOP_I2SO2_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 352 | { .id = TOP_I2SI1_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 353 | /* CLK_CFG_20 */ |
| 354 | { .id = TOP_I2SI2_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 355 | { .id = TOP_DPTX_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 356 | { .id = TOP_AUD_IEC_SEL, .sel = 1 }, /* 1: apll1_ck */ |
| 357 | { .id = TOP_A1SYS_HP_SEL, .sel = 1 }, /* 1: apll1_d4 */ |
| 358 | /* CLK_CFG_21 */ |
| 359 | { .id = TOP_A2SYS_SEL, .sel = 1 }, /* 1: apll2_d4 */ |
| 360 | { .id = TOP_A3SYS_SEL, .sel = 1 }, /* 1: apll3_d4 */ |
| 361 | { .id = TOP_A4SYS_SEL, .sel = 2 }, /* 2: apll4_d4 */ |
| 362 | { .id = TOP_ECC_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */ |
| 363 | /* CLK_CFG_22 */ |
| 364 | { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d6_d8 */ |
| 365 | { .id = TOP_ULPOSC_SEL, .sel = 0 }, /* 3: ulposc_ck */ |
| 366 | { .id = TOP_SRCK_SEL, .sel = 0 }, /* 0: ulposc_d10 */ |
| 367 | }; |
| 368 | |
| 369 | enum pll_id { |
| 370 | APMIXED_ARMPLL_LL, |
| 371 | APMIXED_ARMPLL_BL, |
| 372 | APMIXED_CCIPLL, |
| 373 | APMIXED_ETHPLL, |
| 374 | APMIXED_MSDCPLL, |
| 375 | APMIXED_TVDPLL1, |
| 376 | APMIXED_TVDPLL2, |
| 377 | APMIXED_MMPLL, |
| 378 | APMIXED_MAINPLL, |
| 379 | APMIXED_IMGPLL, |
| 380 | APMIXED_UNIVPLL, |
| 381 | APMIXED_ADSPPLL, |
| 382 | APMIXED_APLL1, |
| 383 | APMIXED_APLL2, |
| 384 | APMIXED_APLL3, |
| 385 | APMIXED_APLL4, |
| 386 | APMIXED_APLL5, |
| 387 | APMIXED_MFGPLL, |
| 388 | APMIXED_PLL_MAX |
| 389 | }; |
| 390 | |
| 391 | static const u32 pll_div_rate[] = { |
| 392 | 3800UL * MHz, |
| 393 | 1900 * MHz, |
| 394 | 950 * MHz, |
| 395 | 475 * MHz, |
| 396 | 237500 * KHz, |
| 397 | 0, |
| 398 | }; |
| 399 | |
| 400 | static const struct pll plls[] = { |
| 401 | PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 402 | NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 403 | pll_div_rate), |
| 404 | PLL(APMIXED_ARMPLL_BL, armpll_bl_con0, armpll_bl_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 405 | NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 406 | pll_div_rate), |
| 407 | PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 408 | NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 409 | pll_div_rate), |
| 410 | PLL(APMIXED_ETHPLL, ethpll_con0, ethpll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 411 | NO_RSTB_SHIFT, 22, ethpll_con1, 24, ethpll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 412 | pll_div_rate), |
| 413 | PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 414 | NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 415 | pll_div_rate), |
| 416 | PLL(APMIXED_TVDPLL1, tvdpll1_con0, tvdpll1_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 417 | NO_RSTB_SHIFT, 22, tvdpll1_con1, 24, tvdpll1_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 418 | pll_div_rate), |
| 419 | PLL(APMIXED_TVDPLL2, tvdpll2_con0, tvdpll2_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 420 | NO_RSTB_SHIFT, 22, tvdpll2_con1, 24, tvdpll2_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 421 | pll_div_rate), |
| 422 | PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 423 | 23, 22, mmpll_con1, 24, mmpll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 424 | pll_div_rate), |
| 425 | PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 426 | 23, 22, mainpll_con1, 24, mainpll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 427 | pll_div_rate), |
| 428 | PLL(APMIXED_IMGPLL, imgpll_con0, imgpll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 429 | NO_RSTB_SHIFT, 22, imgpll_con1, 24, imgpll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 430 | pll_div_rate), |
| 431 | PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 432 | 23, 22, univpll_con1, 24, univpll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 433 | pll_div_rate), |
| 434 | PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 435 | NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 436 | pll_div_rate), |
| 437 | PLL(APMIXED_APLL1, apll1_con0, apll1_con4, |
Johnson Wang | fb660c3 | 2023-02-08 09:46:21 +0800 | [diff] [blame] | 438 | NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 439 | pll_div_rate), |
| 440 | PLL(APMIXED_APLL2, apll2_con0, apll2_con4, |
Johnson Wang | fb660c3 | 2023-02-08 09:46:21 +0800 | [diff] [blame] | 441 | NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 442 | pll_div_rate), |
| 443 | PLL(APMIXED_APLL3, apll3_con0, apll3_con4, |
Johnson Wang | fb660c3 | 2023-02-08 09:46:21 +0800 | [diff] [blame] | 444 | NO_RSTB_SHIFT, 32, apll3_con1, 24, apll3_con2, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 445 | pll_div_rate), |
| 446 | PLL(APMIXED_APLL4, apll4_con0, apll4_con4, |
Johnson Wang | fb660c3 | 2023-02-08 09:46:21 +0800 | [diff] [blame] | 447 | NO_RSTB_SHIFT, 32, apll4_con1, 24, apll4_con2, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 448 | pll_div_rate), |
| 449 | PLL(APMIXED_APLL5, apll5_con0, apll5_con4, |
Johnson Wang | fb660c3 | 2023-02-08 09:46:21 +0800 | [diff] [blame] | 450 | NO_RSTB_SHIFT, 32, apll5_con1, 24, apll5_con2, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 451 | pll_div_rate), |
| 452 | PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3, |
Garmin Chang | d9b1dfe | 2022-09-11 21:12:16 +0800 | [diff] [blame] | 453 | NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0, |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 454 | pll_div_rate), |
| 455 | }; |
| 456 | |
| 457 | struct rate { |
| 458 | enum pll_id id; |
| 459 | u32 rate; |
| 460 | }; |
| 461 | |
| 462 | static const struct rate rates[] = { |
| 463 | { .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ }, |
| 464 | { .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ }, |
| 465 | { .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ }, |
| 466 | { .id = APMIXED_ETHPLL, .rate = ETHPLL_HZ }, |
| 467 | { .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ }, |
| 468 | { .id = APMIXED_TVDPLL1, .rate = TVDPLL1_HZ }, |
| 469 | { .id = APMIXED_TVDPLL2, .rate = TVDPLL2_HZ }, |
| 470 | { .id = APMIXED_MMPLL, .rate = MMPLL_HZ }, |
| 471 | { .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ }, |
| 472 | { .id = APMIXED_IMGPLL, .rate = IMGPLL_HZ }, |
| 473 | { .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ }, |
| 474 | { .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ }, |
| 475 | { .id = APMIXED_APLL1, .rate = APLL1_HZ }, |
| 476 | { .id = APMIXED_APLL2, .rate = APLL2_HZ }, |
| 477 | { .id = APMIXED_APLL3, .rate = APLL3_HZ }, |
| 478 | { .id = APMIXED_APLL4, .rate = APLL4_HZ }, |
| 479 | { .id = APMIXED_APLL5, .rate = APLL5_HZ }, |
| 480 | { .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ }, |
| 481 | }; |
| 482 | |
| 483 | void pll_set_pcw_change(const struct pll *pll) |
| 484 | { |
| 485 | setbits32(pll->div_reg, PLL_PCW_CHG); |
| 486 | } |
| 487 | |
| 488 | void mt_pll_init(void) |
| 489 | { |
| 490 | int i; |
| 491 | |
| 492 | /* enable clock square */ |
| 493 | setbits32(&mtk_apmixed->ap_pll_con0, BIT(2)); |
| 494 | |
| 495 | udelay(PLL_CKSQ_ON_DELAY); |
| 496 | |
| 497 | /* enable clock square1 low-pass filter */ |
| 498 | setbits32(&mtk_apmixed->ap_pll_con0, BIT(1)); |
| 499 | |
| 500 | /* |
| 501 | * BIT(3): 1 for register control; 0 for sleep control |
| 502 | * BIT(8): 1 to enable clock square2; 0 to disable it |
| 503 | */ |
| 504 | clrbits32(&mtk_apmixed->ap_pll_con0, BIT(3) | BIT(8)); |
| 505 | |
| 506 | /* xPLL PWR ON */ |
| 507 | for (i = 0; i < APMIXED_PLL_MAX; i++) |
| 508 | setbits32(plls[i].pwr_reg, PLL_PWR_ON); |
| 509 | |
| 510 | udelay(PLL_PWR_ON_DELAY); |
| 511 | |
| 512 | /* xPLL ISO Disable */ |
| 513 | for (i = 0; i < APMIXED_PLL_MAX; i++) |
| 514 | clrbits32(plls[i].pwr_reg, PLL_ISO); |
| 515 | |
| 516 | udelay(PLL_ISO_DELAY); |
| 517 | |
| 518 | /* disable glitch free if rate < 374MHz */ |
| 519 | for (i = 0; i < ARRAY_SIZE(rates); i++) { |
| 520 | if (rates[i].rate < 374 * MHz) |
| 521 | clrbits32(plls[rates[i].id].reg, GLITCH_FREE_EN); |
| 522 | } |
| 523 | |
| 524 | /* disable mfg_ck_en[20], enable mfg_opp_ck_en[2] */ |
Johnson Wang | 70f30af | 2022-08-30 16:56:43 +0800 | [diff] [blame] | 525 | clrsetbits32(&mtk_apmixed->mfgpll_con0, BIT(20), BIT(2)); |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 526 | |
| 527 | /* xPLL Frequency Set */ |
| 528 | for (i = 0; i < ARRAY_SIZE(rates); i++) |
| 529 | pll_set_rate(&plls[rates[i].id], rates[i].rate); |
| 530 | |
| 531 | /* AUDPLL Tuner Frequency Set */ |
| 532 | write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con3) + 1); |
| 533 | write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con3) + 1); |
| 534 | write32(&mtk_apmixed->apll3_tuner_con0, read32(&mtk_apmixed->apll3_con3) + 1); |
| 535 | write32(&mtk_apmixed->apll4_tuner_con0, read32(&mtk_apmixed->apll4_con3) + 1); |
| 536 | write32(&mtk_apmixed->apll5_tuner_con0, read32(&mtk_apmixed->apll5_con3) + 1); |
| 537 | |
| 538 | /* xPLL Frequency Enable */ |
| 539 | for (i = 0; i < APMIXED_PLL_MAX; i++) { |
| 540 | if (i == APMIXED_APLL5) |
| 541 | setbits32(plls[i].pwr_reg, MT8188_APLL5_EN); |
| 542 | else |
| 543 | setbits32(plls[i].reg, MT8188_PLL_EN); |
| 544 | } |
| 545 | |
| 546 | /* enable univpll analog divider=13 */ |
| 547 | setbits32(&mtk_apmixed->univpll_con0, 0x8d); |
| 548 | |
| 549 | /* wait for PLL stable */ |
| 550 | udelay(PLL_EN_DELAY); |
| 551 | |
| 552 | /* xPLL DIV Enable & RSTB */ |
| 553 | for (i = 0; i < APMIXED_PLL_MAX; i++) { |
| 554 | if (plls[i].rstb_shift != NO_RSTB_SHIFT) { |
| 555 | setbits32(plls[i].reg, PLL_DIV_EN); |
| 556 | setbits32(plls[i].reg, 1 << plls[i].rstb_shift); |
| 557 | } |
| 558 | } |
| 559 | |
| 560 | /* MCUCFG CLKMUX */ |
| 561 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1); |
| 562 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1); |
| 563 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1); |
| 564 | |
| 565 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
| 566 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
| 567 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
| 568 | |
| 569 | /* initialize SPM request */ |
| 570 | setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); |
| 571 | |
| 572 | /* |
| 573 | * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! |
| 574 | */ |
| 575 | for (i = 0; i < ARRAY_SIZE(mux_sels); i++) |
Rex-BC Chen | a6cd1bd | 2022-10-18 18:59:41 +0800 | [diff] [blame] | 576 | pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 577 | |
| 578 | /* turn off unused clock in infra_ao */ |
| 579 | write32(&mt8188_infracfg_ao->module_sw_cg_1_set, 0x00004000); |
| 580 | write32(&mt8188_infracfg_ao->module_sw_cg_2_set, 0xf0003802); |
| 581 | write32(&mt8188_infracfg_ao->module_sw_cg_3_set, 0x30000000); |
| 582 | write32(&mt8188_infracfg_ao->module_sw_cg_4_set, 0x81c20000); |
| 583 | } |
| 584 | |
| 585 | void mt_pll_raise_little_cpu_freq(u32 freq) |
| 586 | { |
| 587 | /* switch clock source to intermediate clock */ |
| 588 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_26M); |
| 589 | |
| 590 | /* disable armpll_ll frequency output */ |
| 591 | clrbits32(plls[APMIXED_ARMPLL_LL].reg, MT8188_PLL_EN); |
| 592 | |
| 593 | /* raise armpll_ll frequency */ |
| 594 | pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); |
| 595 | |
| 596 | /* enable armpll_ll frequency output */ |
| 597 | setbits32(plls[APMIXED_ARMPLL_LL].reg, MT8188_PLL_EN); |
| 598 | udelay(PLL_EN_DELAY); |
| 599 | |
| 600 | /* switch clock source back to armpll_ll */ |
| 601 | clrsetbits32(&mtk_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
| 602 | } |
| 603 | |
| 604 | void mt_pll_raise_cci_freq(u32 freq) |
| 605 | { |
| 606 | /* switch clock source to intermediate clock */ |
| 607 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_26M); |
| 608 | |
| 609 | /* disable ccipll frequency output */ |
| 610 | clrbits32(plls[APMIXED_CCIPLL].reg, MT8188_PLL_EN); |
| 611 | |
| 612 | /* raise ccipll frequency */ |
| 613 | pll_set_rate(&plls[APMIXED_CCIPLL], freq); |
| 614 | |
| 615 | /* enable ccipll frequency output */ |
| 616 | setbits32(plls[APMIXED_CCIPLL].reg, MT8188_PLL_EN); |
| 617 | udelay(PLL_EN_DELAY); |
| 618 | |
| 619 | /* switch clock source back to ccipll */ |
| 620 | clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL); |
| 621 | } |
| 622 | |
| 623 | void mt_pll_set_tvd_pll1_freq(u32 freq) |
| 624 | { |
| 625 | /* disable tvdpll frequency output */ |
| 626 | clrbits32(plls[APMIXED_TVDPLL1].reg, MT8188_PLL_EN); |
| 627 | |
| 628 | /* set tvdpll frequency */ |
| 629 | pll_set_rate(&plls[APMIXED_TVDPLL1], freq); |
| 630 | |
| 631 | /* enable tvdpll frequency output */ |
| 632 | setbits32(plls[APMIXED_TVDPLL1].reg, MT8188_PLL_EN); |
| 633 | udelay(PLL_EN_DELAY); |
| 634 | } |
| 635 | |
Rex-BC Chen | a6cd1bd | 2022-10-18 18:59:41 +0800 | [diff] [blame] | 636 | void mt_pll_edp_mux_set_sel(u32 sel) |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 637 | { |
Rex-BC Chen | a6cd1bd | 2022-10-18 18:59:41 +0800 | [diff] [blame] | 638 | pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel); |
garmin chang | 4e8a1ec | 2022-06-08 14:20:58 +0800 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | void mt_pll_set_usb_clock(void) |
| 642 | { |
| 643 | /* port0 */ |
| 644 | setbits32(&mt8188_pericfg_ao->peri_module_sw_cg_0_clr, BIT(9) | BIT(10)); |
| 645 | setbits32(&mtk_topckgen->clk_misc_cfg_3, BIT(3) | BIT(5)); |
| 646 | |
| 647 | /* port1 sys clk */ |
| 648 | setbits32(&mtk_topckgen->clk_cfg_10_clr, BIT(15)); |
| 649 | setbits32(&mtk_topckgen->clk_cfg_10_set, BIT(8)); |
| 650 | setbits32(&mtk_topckgen->clk_cfg_update1, BIT(9)); |
| 651 | setbits32(&mt8188_pericfg_ao->peri_module_sw_cg_0_clr, BIT(13)); |
| 652 | |
| 653 | /* port1 xhci clk */ |
| 654 | setbits32(&mtk_topckgen->clk_cfg_10_clr, BIT(23)); |
| 655 | setbits32(&mtk_topckgen->clk_cfg_10_set, BIT(16)); |
| 656 | setbits32(&mtk_topckgen->clk_cfg_update1, BIT(10)); |
| 657 | setbits32(&mt8188_pericfg_ao->peri_module_sw_cg_0_clr, BIT(14)); |
| 658 | |
| 659 | setbits32(&mtk_topckgen->clk_misc_cfg_3, BIT(2) | BIT(4)); |
| 660 | } |
| 661 | |
| 662 | u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) |
| 663 | { |
| 664 | u32 output, count, clk_dbg_cfg, clk_misc_cfg_0; |
| 665 | u32 multiplier = 1; |
| 666 | |
| 667 | /* backup */ |
| 668 | clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); |
| 669 | clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); |
| 670 | |
| 671 | /* set up frequency meter */ |
| 672 | if (type == FMETER_ABIST) { |
| 673 | SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, |
| 674 | CLK_DBG_CFG_ABIST_CK_SEL, id, |
| 675 | CLK_DBG_CFG_CKGEN_CK_SEL, 0, |
| 676 | CLK_DBG_CFG_METER_CK_SEL, 0, |
| 677 | CLK_DBG_CFG_CKGEN_EN, 0); |
| 678 | SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, |
| 679 | CLK_MISC_CFG_0_METER_DIV, 3); |
| 680 | multiplier = 4; |
| 681 | } else if (type == FMETER_CKGEN) { |
| 682 | SET32_BITFIELDS(&mtk_topckgen->clk_dbg_cfg, |
| 683 | CLK_DBG_CFG_ABIST_CK_SEL, 0, |
| 684 | CLK_DBG_CFG_CKGEN_CK_SEL, id, |
| 685 | CLK_DBG_CFG_METER_CK_SEL, 1, |
| 686 | CLK_DBG_CFG_CKGEN_EN, 1); |
| 687 | SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, |
| 688 | CLK_MISC_CFG_0_METER_DIV, 0); |
| 689 | } else { |
| 690 | die("unsupported fmeter type\n"); |
| 691 | } |
| 692 | |
| 693 | /* enable frequency meter */ |
| 694 | write32(&mtk_topckgen->clk26cali_0, 0x80); |
| 695 | |
| 696 | /* set load count = 1024-1 */ |
| 697 | SET32_BITFIELDS(&mtk_topckgen->clk26cali_1, CLK26CALI_1_LOAD_CNT, 0x3ff); |
| 698 | |
| 699 | /* trigger frequency meter */ |
| 700 | SET32_BITFIELDS(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER, 1); |
| 701 | |
| 702 | /* wait frequency meter until finished */ |
| 703 | if (wait_us(200, !READ32_BITFIELD(&mtk_topckgen->clk26cali_0, CLK26CALI_0_TRIGGER))) { |
| 704 | count = read32(&mtk_topckgen->clk26cali_1) & 0xffff; |
| 705 | output = (count * 26000) / 1024; /* KHz */ |
| 706 | } else { |
| 707 | printk(BIOS_WARNING, "fmeter timeout\n"); |
| 708 | output = 0; |
| 709 | } |
| 710 | |
| 711 | /* disable frequency meter */ |
| 712 | write32(&mtk_topckgen->clk26cali_0, 0x0000); |
| 713 | |
| 714 | /* restore */ |
| 715 | write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); |
| 716 | write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); |
| 717 | |
| 718 | return output * multiplier; |
| 719 | } |