Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 4c0dc4ee918c3046719af868999785a381f06cc5 / src / soc / mediatek / mt8188 / pll.c
  1. 4c0dc4e soc/mediatek/mt8188: Support 4K resolution display by Hsiao Chien Sung · 1 year, 5 months ago
  2. fb660c3 soc/mediatek/mt8188: Fix audio sampling rate by Johnson Wang · 1 year, 6 months ago
  3. a6cd1bd soc/mediatek: Unify PLL function names by Rex-BC Chen · 1 year, 10 months ago
  4. 1fac2e2 soc/mediatek/mt8188: Set PLLs to hardware default values by Garmin Chang · 2 years ago
  5. f189249 soc/mediatek/mt8188: Fix indention in pll.c by Garmin.Chang · 2 years ago
  6. c7b549e soc/mediatek/mt8188: Change vpp_sel default mux for 4k support by Garmin Chang · 2 years ago
  7. d9b1dfe soc/mediatek/mt8188: Fix some wrong settings for PLLs by Garmin Chang · 2 years ago
  8. 70f30af soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes by Johnson Wang · 2 years ago
  9. 577766e soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MIT by Macpaul Lin · 2 years ago
  10. 4e8a1ec soc/mediatek/mt8188: Add PLL and clock init support by garmin chang · 2 years, 2 months ago