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review.coreboot.org / coreboot / 4b42983c7a072011499e6a610cfccf3d30689b05 / . / src / northbridge / intel / x4x / acpi / hostbridge.asl
blob: 0126aaf0a76510ecd2bec3083f38ad37902fd9aa [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Damien Zammit43a1f782015-08-19 15:16:59 +1000[diff] [blame]3
4#include <arch/ioapic.h>
5
6Name(_HID,EISAID("PNP0A08")) // PCIe
7Name(_CID,EISAID("PNP0A03")) // PCI
8
Damien Zammit43a1f782015-08-19 15:16:59 +1000[diff] [blame]9Name(_BBN, 0)
10
11Device (MCHC)
12{
13 Name(_ADR, 0x00000000) // 0:0.0
14
15 OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
16 Field (MCHP, DWordAcc, NoLock, Preserve)
17 {
18 Offset (0x40), // EPBAR
19 EPEN, 1, // Enable
20 , 11, //
21 EPBR, 24, // EPBAR
22
23 Offset (0x48), // MCHBAR
24 MHEN, 1, // Enable
25 , 13, //
26 MHBR, 22, // MCHBAR
27
28 Offset (0x60), // PCIe BAR
29 PXEN, 1, // Enable
30 PXSZ, 2, // BAR size
31 , 23, //
32 PXBR, 10, // PCIe BAR
33
34 Offset (0x68), // DMIBAR
35 DMEN, 1, // Enable
36 , 11, //
37 DMBR, 24, // DMIBAR
38
39 // ...
40
41 Offset (0x90), // PAM0
42 , 4,
43 PM0H, 2,
44 , 2,
45 Offset (0x91), // PAM1
46 PM1L, 2,
47 , 2,
48 PM1H, 2,
49 , 2,
50 Offset (0x92), // PAM2
51 PM2L, 2,
52 , 2,
53 PM2H, 2,
54 , 2,
55 Offset (0x93), // PAM3
56 PM3L, 2,
57 , 2,
58 PM3H, 2,
59 , 2,
60 Offset (0x94), // PAM4
61 PM4L, 2,
62 , 2,
63 PM4H, 2,
64 , 2,
65 Offset (0x95), // PAM5
66 PM5L, 2,
67 , 2,
68 PM5H, 2,
69 , 2,
70 Offset (0x96), // PAM6
71 PM6L, 2,
72 , 2,
73 PM6H, 2,
74 , 2,
75
76 Offset (0xa0), // Top of Used Memory
77 TOM, 8,
78
79 Offset (0xb0), // Top of Low Used Memory
80 , 4,
81 TLUD, 12,
82 }
83
84}
85
86Name (MCRS, ResourceTemplate()
87{
88 // Bus Numbers
89 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
90 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
91
92 // IO Region 0
93 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
94 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
95
96 // PCI Config Space
97 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
98
99 // IO Region 1
100 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
101 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
102
103 // VGA memory (0xa0000-0xbffff)
104 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
105 Cacheable, ReadWrite,
106 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
107 0x00020000,,, ASEG)
108
109 // OPROM reserved (0xc0000-0xc3fff)
110 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
111 Cacheable, ReadWrite,
112 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
113 0x00004000,,, OPR0)
114
115 // OPROM reserved (0xc4000-0xc7fff)
116 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
117 Cacheable, ReadWrite,
118 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
119 0x00004000,,, OPR1)
120
121 // OPROM reserved (0xc8000-0xcbfff)
122 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
123 Cacheable, ReadWrite,
124 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
125 0x00004000,,, OPR2)
126
127 // OPROM reserved (0xcc000-0xcffff)
128 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
129 Cacheable, ReadWrite,
130 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
131 0x00004000,,, OPR3)
132
133 // OPROM reserved (0xd0000-0xd3fff)
134 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
135 Cacheable, ReadWrite,
136 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
137 0x00004000,,, OPR4)
138
139 // OPROM reserved (0xd4000-0xd7fff)
140 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
141 Cacheable, ReadWrite,
142 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
143 0x00004000,,, OPR5)
144
145 // OPROM reserved (0xd8000-0xdbfff)
146 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
147 Cacheable, ReadWrite,
148 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
149 0x00004000,,, OPR6)
150
151 // OPROM reserved (0xdc000-0xdffff)
152 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
153 Cacheable, ReadWrite,
154 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
155 0x00004000,,, OPR7)
156
157 // BIOS Extension (0xe0000-0xe3fff)
158 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
159 Cacheable, ReadWrite,
160 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
161 0x00004000,,, ESG0)
162
163 // BIOS Extension (0xe4000-0xe7fff)
164 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
165 Cacheable, ReadWrite,
166 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
167 0x00004000,,, ESG1)
168
169 // BIOS Extension (0xe8000-0xebfff)
170 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
171 Cacheable, ReadWrite,
172 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
173 0x00004000,,, ESG2)
174
175 // BIOS Extension (0xec000-0xeffff)
176 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
177 Cacheable, ReadWrite,
178 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
179 0x00004000,,, ESG3)
180
181 // System BIOS (0xf0000-0xfffff)
182 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
183 Cacheable, ReadWrite,
184 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
185 0x00010000,,, FSEG)
186
187 // PCI Memory Region (Top of memory-0xfebfffff)
188 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
189 Cacheable, ReadWrite,
190 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
191 IO_APIC_ADDR,,, PM01)
192
193 // TPM Area (0xfed40000-0xfed44fff)
194 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
195 Cacheable, ReadWrite,
196 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
197 0x00005000,,, TPMR)
198})
199
200// Current Resource Settings
201
202Method (_CRS, 0, Serialized)
203{
204 // Find PCI resource area in MCRS
205 CreateDwordField(MCRS, ^PM01._MIN, PMIN)
206 CreateDwordField(MCRS, ^PM01._MAX, PMAX)
207 CreateDwordField(MCRS, ^PM01._LEN, PLEN)
208
209 // Fix up PCI memory region:
210 // Enter actual TOLUD. The TOLUD register contains bits 20-31 of
211 // the top of memory address.
212 ShiftLeft (^MCHC.TLUD, 20, PMIN)
213 Add(Subtract(PMAX, PMIN), 1, PLEN)
214
215 Return (MCRS)
216}