Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; version 2 of |
| 8 | * the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/ioapic.h> |
| 17 | |
| 18 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 19 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 20 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 21 | Name(_BBN, 0) |
| 22 | |
| 23 | Device (MCHC) |
| 24 | { |
| 25 | Name(_ADR, 0x00000000) // 0:0.0 |
| 26 | |
| 27 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 28 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 29 | { |
| 30 | Offset (0x40), // EPBAR |
| 31 | EPEN, 1, // Enable |
| 32 | , 11, // |
| 33 | EPBR, 24, // EPBAR |
| 34 | |
| 35 | Offset (0x48), // MCHBAR |
| 36 | MHEN, 1, // Enable |
| 37 | , 13, // |
| 38 | MHBR, 22, // MCHBAR |
| 39 | |
| 40 | Offset (0x60), // PCIe BAR |
| 41 | PXEN, 1, // Enable |
| 42 | PXSZ, 2, // BAR size |
| 43 | , 23, // |
| 44 | PXBR, 10, // PCIe BAR |
| 45 | |
| 46 | Offset (0x68), // DMIBAR |
| 47 | DMEN, 1, // Enable |
| 48 | , 11, // |
| 49 | DMBR, 24, // DMIBAR |
| 50 | |
| 51 | // ... |
| 52 | |
| 53 | Offset (0x90), // PAM0 |
| 54 | , 4, |
| 55 | PM0H, 2, |
| 56 | , 2, |
| 57 | Offset (0x91), // PAM1 |
| 58 | PM1L, 2, |
| 59 | , 2, |
| 60 | PM1H, 2, |
| 61 | , 2, |
| 62 | Offset (0x92), // PAM2 |
| 63 | PM2L, 2, |
| 64 | , 2, |
| 65 | PM2H, 2, |
| 66 | , 2, |
| 67 | Offset (0x93), // PAM3 |
| 68 | PM3L, 2, |
| 69 | , 2, |
| 70 | PM3H, 2, |
| 71 | , 2, |
| 72 | Offset (0x94), // PAM4 |
| 73 | PM4L, 2, |
| 74 | , 2, |
| 75 | PM4H, 2, |
| 76 | , 2, |
| 77 | Offset (0x95), // PAM5 |
| 78 | PM5L, 2, |
| 79 | , 2, |
| 80 | PM5H, 2, |
| 81 | , 2, |
| 82 | Offset (0x96), // PAM6 |
| 83 | PM6L, 2, |
| 84 | , 2, |
| 85 | PM6H, 2, |
| 86 | , 2, |
| 87 | |
| 88 | Offset (0xa0), // Top of Used Memory |
| 89 | TOM, 8, |
| 90 | |
| 91 | Offset (0xb0), // Top of Low Used Memory |
| 92 | , 4, |
| 93 | TLUD, 12, |
| 94 | } |
| 95 | |
| 96 | } |
| 97 | |
| 98 | Name (MCRS, ResourceTemplate() |
| 99 | { |
| 100 | // Bus Numbers |
| 101 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 102 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 103 | |
| 104 | // IO Region 0 |
| 105 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 106 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 107 | |
| 108 | // PCI Config Space |
| 109 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 110 | |
| 111 | // IO Region 1 |
| 112 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 113 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 114 | |
| 115 | // VGA memory (0xa0000-0xbffff) |
| 116 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 117 | Cacheable, ReadWrite, |
| 118 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 119 | 0x00020000,,, ASEG) |
| 120 | |
| 121 | // OPROM reserved (0xc0000-0xc3fff) |
| 122 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 123 | Cacheable, ReadWrite, |
| 124 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 125 | 0x00004000,,, OPR0) |
| 126 | |
| 127 | // OPROM reserved (0xc4000-0xc7fff) |
| 128 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 129 | Cacheable, ReadWrite, |
| 130 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 131 | 0x00004000,,, OPR1) |
| 132 | |
| 133 | // OPROM reserved (0xc8000-0xcbfff) |
| 134 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 135 | Cacheable, ReadWrite, |
| 136 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 137 | 0x00004000,,, OPR2) |
| 138 | |
| 139 | // OPROM reserved (0xcc000-0xcffff) |
| 140 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 141 | Cacheable, ReadWrite, |
| 142 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 143 | 0x00004000,,, OPR3) |
| 144 | |
| 145 | // OPROM reserved (0xd0000-0xd3fff) |
| 146 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 147 | Cacheable, ReadWrite, |
| 148 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 149 | 0x00004000,,, OPR4) |
| 150 | |
| 151 | // OPROM reserved (0xd4000-0xd7fff) |
| 152 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 153 | Cacheable, ReadWrite, |
| 154 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 155 | 0x00004000,,, OPR5) |
| 156 | |
| 157 | // OPROM reserved (0xd8000-0xdbfff) |
| 158 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 159 | Cacheable, ReadWrite, |
| 160 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 161 | 0x00004000,,, OPR6) |
| 162 | |
| 163 | // OPROM reserved (0xdc000-0xdffff) |
| 164 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 165 | Cacheable, ReadWrite, |
| 166 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 167 | 0x00004000,,, OPR7) |
| 168 | |
| 169 | // BIOS Extension (0xe0000-0xe3fff) |
| 170 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 171 | Cacheable, ReadWrite, |
| 172 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 173 | 0x00004000,,, ESG0) |
| 174 | |
| 175 | // BIOS Extension (0xe4000-0xe7fff) |
| 176 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 177 | Cacheable, ReadWrite, |
| 178 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 179 | 0x00004000,,, ESG1) |
| 180 | |
| 181 | // BIOS Extension (0xe8000-0xebfff) |
| 182 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 183 | Cacheable, ReadWrite, |
| 184 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 185 | 0x00004000,,, ESG2) |
| 186 | |
| 187 | // BIOS Extension (0xec000-0xeffff) |
| 188 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 189 | Cacheable, ReadWrite, |
| 190 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 191 | 0x00004000,,, ESG3) |
| 192 | |
| 193 | // System BIOS (0xf0000-0xfffff) |
| 194 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 195 | Cacheable, ReadWrite, |
| 196 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 197 | 0x00010000,,, FSEG) |
| 198 | |
| 199 | // PCI Memory Region (Top of memory-0xfebfffff) |
| 200 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 201 | Cacheable, ReadWrite, |
| 202 | 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, |
| 203 | IO_APIC_ADDR,,, PM01) |
| 204 | |
| 205 | // TPM Area (0xfed40000-0xfed44fff) |
| 206 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 207 | Cacheable, ReadWrite, |
| 208 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 209 | 0x00005000,,, TPMR) |
| 210 | }) |
| 211 | |
| 212 | // Current Resource Settings |
| 213 | |
| 214 | Method (_CRS, 0, Serialized) |
| 215 | { |
| 216 | // Find PCI resource area in MCRS |
| 217 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 218 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 219 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
| 220 | |
| 221 | // Fix up PCI memory region: |
| 222 | // Enter actual TOLUD. The TOLUD register contains bits 20-31 of |
| 223 | // the top of memory address. |
| 224 | ShiftLeft (^MCHC.TLUD, 20, PMIN) |
| 225 | Add(Subtract(PMAX, PMIN), 1, PLEN) |
| 226 | |
| 227 | Return (MCRS) |
| 228 | } |