blob: ebb6eb9bddc72b28a445256860eeea98fe42a18c [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Damien Zammitf7060f12015-11-14 00:59:21 +11003
4#include "hostbridge.asl"
5#include "../iomap.h"
Elyes HAOUAS4ec67fc2019-10-30 12:39:17 +01006#include <southbridge/intel/common/rcba.h>
Damien Zammitf7060f12015-11-14 00:59:21 +11007
8/* PCI Device Resource Consumption */
9Device (PDRC)
10{
11 Name (_HID, EISAID("PNP0C02"))
12 Name (_UID, 1)
13
14 /* This does not seem to work correctly yet - set values statically for
15 * now.
16 */
17
18 Name (PDRS, ResourceTemplate() {
Elyes HAOUAS4ec67fc2019-10-30 12:39:17 +010019 Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
Damien Zammitf7060f12015-11-14 00:59:21 +110020 Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
21 Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
22 Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Kyösti Mälkki503d3242019-03-05 07:54:28 +020023 Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
Damien Zammitf7060f12015-11-14 00:59:21 +110024 Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
25 Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
26 Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
27 })
28
29 /* Current Resource Settings */
30 Method (_CRS, 0, Serialized)
31 {
32 Return(PDRS)
33 }
34}
35
36// PCIe graphics port 0:1.0
37#include "peg.asl"